Greg Kroah-Hartman
598cf27219
Link: https://lore.kernel.org/r/20260217200002.683975158@linuxfoundation.org Tested-by: Florian Fainelli <florian.fainelli@broadcom.com> Tested-by: Takeshi Ogasawara <takeshi.ogasawara@futuring-girl.com> Tested-by: Peter Schneider <pschneider1968@googlemail.com> Tested-by: Jon Hunter <jonathanh@nvidia.com> Tested-by: Salvatore Bonaccorso <carnil@debian.org> Tested-by: Brett A C Sheffield <bacs@librecast.net> Tested-by: Mark Brown <broonie@kernel.org> Tested-by: Luna Jernberg <droidbittin@gmail.com> Tested-by: Ronald Warsow <rwarsow@gmx.de> Tested-by: Justin M. Forbes <jforbes@fedoraproject.org> Tested-by: Ron Economos <re@w6rz.net> Tested-by: Miguel Ojeda <ojeda@kernel.org> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
73 lines
3.3 KiB
C
73 lines
3.3 KiB
C
// SPDX-License-Identifier: GPL-2.0-or-later
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/*
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* Copyright 1998-2008 VIA Technologies, Inc. All Rights Reserved.
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* Copyright 2001-2008 S3 Graphics, Inc. All Rights Reserved.
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*/
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#include "global.h"
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struct GFX_DPA_SETTING GFX_DPA_SETTING_TBL_VT3324[] = {
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/* ClkRange, DVP0, DVP0DataDriving, DVP0ClockDriving, DVP1,
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DVP1Driving, DFPHigh, DFPLow */
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/* CR96, SR2A[5], SR1B[1], SR2A[4], SR1E[2], CR9B,
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SR65, CR97, CR99 */
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/* LCK/VCK < 30000000 will use this value */
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{DPA_CLK_RANGE_30M, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00,
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0x00},
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/* 30000000 < LCK/VCK < 50000000 will use this value */
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{DPA_CLK_RANGE_30_50M, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00,
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0x00},
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/* 50000000 < LCK/VCK < 70000000 will use this value */
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{DPA_CLK_RANGE_50_70M, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, 0x00, 0x00,
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0x00},
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/* 70000000 < LCK/VCK < 100000000 will use this value */
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{DPA_CLK_RANGE_70_100M, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, 0x00, 0x00,
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0x00},
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/* 100000000 < LCK/VCK < 15000000 will use this value */
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{DPA_CLK_RANGE_100_150M, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, 0x00, 0x00,
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0x00},
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/* 15000000 < LCK/VCK will use this value */
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{DPA_CLK_RANGE_150M, 0x00, 0x00, 0x00, 0x00, 0x00, 0x08, 0x0E, 0x00,
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0x00},
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};
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struct GFX_DPA_SETTING GFX_DPA_SETTING_TBL_VT3327[] = {
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/* ClkRange,DVP0, DVP0DataDriving, DVP0ClockDriving, DVP1,
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DVP1Driving, DFPHigh, DFPLow */
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/* CR96, SR2A[5], SR1B[1], SR2A[4], SR1E[2], CR9B,
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SR65, CR97, CR99 */
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/* LCK/VCK < 30000000 will use this value */
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{DPA_CLK_RANGE_30M, 0x07, 0x00, 0x00, 0x00, 0x00, 0x03, 0x00, 0x08, 0x01},
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/* 30000000 < LCK/VCK < 50000000 will use this value */
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{DPA_CLK_RANGE_30_50M, 0x07, 0x00, 0x00, 0x00, 0x00, 0x03, 0x00, 0x08, 0x01},
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/* 50000000 < LCK/VCK < 70000000 will use this value */
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{DPA_CLK_RANGE_50_70M, 0x06, 0x00, 0x00, 0x00, 0x00, 0x03, 0x00, 0x08, 0x01},
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/* 70000000 < LCK/VCK < 100000000 will use this value */
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{DPA_CLK_RANGE_70_100M, 0x03, 0x00, 0x00, 0x00, 0x00, 0x03, 0x00, 0x08, 0x03},
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/* 100000000 < LCK/VCK < 15000000 will use this value */
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{DPA_CLK_RANGE_100_150M, 0x03, 0x00, 0x00, 0x00, 0x00, 0x03, 0x00, 0x01, 0x02},
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/* 15000000 < LCK/VCK will use this value */
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{DPA_CLK_RANGE_150M, 0x00, 0x20, 0x00, 0x10, 0x00, 0x03, 0x00, 0x0D, 0x03},
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};
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/* For VT3364: */
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struct GFX_DPA_SETTING GFX_DPA_SETTING_TBL_VT3364[] = {
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/* ClkRange,DVP0, DVP0DataDriving, DVP0ClockDriving, DVP1,
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DVP1Driving, DFPHigh, DFPLow */
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/* CR96, SR2A[5], SR1B[1], SR2A[4], SR1E[2], CR9B,
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SR65, CR97, CR99 */
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/* LCK/VCK < 30000000 will use this value */
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{DPA_CLK_RANGE_30M, 0x07, 0x00, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x08},
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/* 30000000 < LCK/VCK < 50000000 will use this value */
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{DPA_CLK_RANGE_30_50M, 0x07, 0x00, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x08},
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/* 50000000 < LCK/VCK < 70000000 will use this value */
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{DPA_CLK_RANGE_50_70M, 0x07, 0x00, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x08},
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/* 70000000 < LCK/VCK < 100000000 will use this value */
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{DPA_CLK_RANGE_70_100M, 0x07, 0x00, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x08},
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/* 100000000 < LCK/VCK < 15000000 will use this value */
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{DPA_CLK_RANGE_100_150M, 0x03, 0x00, 0x02, 0x00, 0x00, 0x03, 0x00, 0x00, 0x08},
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/* 15000000 < LCK/VCK will use this value */
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{DPA_CLK_RANGE_150M, 0x01, 0x00, 0x02, 0x10, 0x00, 0x03, 0x00, 0x00, 0x08},
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};
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