Greg Kroah-Hartman
598cf27219
Link: https://lore.kernel.org/r/20260217200002.683975158@linuxfoundation.org Tested-by: Florian Fainelli <florian.fainelli@broadcom.com> Tested-by: Takeshi Ogasawara <takeshi.ogasawara@futuring-girl.com> Tested-by: Peter Schneider <pschneider1968@googlemail.com> Tested-by: Jon Hunter <jonathanh@nvidia.com> Tested-by: Salvatore Bonaccorso <carnil@debian.org> Tested-by: Brett A C Sheffield <bacs@librecast.net> Tested-by: Mark Brown <broonie@kernel.org> Tested-by: Luna Jernberg <droidbittin@gmail.com> Tested-by: Ronald Warsow <rwarsow@gmx.de> Tested-by: Justin M. Forbes <jforbes@fedoraproject.org> Tested-by: Ron Economos <re@w6rz.net> Tested-by: Miguel Ojeda <ojeda@kernel.org> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
49 lines
1.6 KiB
C
49 lines
1.6 KiB
C
/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
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/*
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* Copyright (c) 2021, The Linux Foundation. All rights reserved.
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*/
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#ifndef _DT_BINDINGS_CLK_QCOM_LPASS_AUDIO_CC_SC7280_H
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#define _DT_BINDINGS_CLK_QCOM_LPASS_AUDIO_CC_SC7280_H
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/* LPASS_AUDIO_CC clocks */
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#define LPASS_AUDIO_CC_PLL 0
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#define LPASS_AUDIO_CC_PLL_OUT_AUX2 1
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#define LPASS_AUDIO_CC_PLL_OUT_AUX2_DIV_CLK_SRC 2
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#define LPASS_AUDIO_CC_PLL_OUT_MAIN_DIV_CLK_SRC 3
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#define LPASS_AUDIO_CC_CDIV_RX_MCLK_DIV_CLK_SRC 4
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#define LPASS_AUDIO_CC_CODEC_MEM0_CLK 5
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#define LPASS_AUDIO_CC_CODEC_MEM1_CLK 6
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#define LPASS_AUDIO_CC_CODEC_MEM2_CLK 7
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#define LPASS_AUDIO_CC_CODEC_MEM_CLK 8
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#define LPASS_AUDIO_CC_EXT_MCLK0_CLK 9
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#define LPASS_AUDIO_CC_EXT_MCLK0_CLK_SRC 10
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#define LPASS_AUDIO_CC_EXT_MCLK1_CLK 11
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#define LPASS_AUDIO_CC_EXT_MCLK1_CLK_SRC 12
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#define LPASS_AUDIO_CC_RX_MCLK_2X_CLK 13
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#define LPASS_AUDIO_CC_RX_MCLK_CLK 14
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#define LPASS_AUDIO_CC_RX_MCLK_CLK_SRC 15
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/* LPASS AUDIO CC CSR */
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#define LPASS_AUDIO_SWR_RX_CGCR 0
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#define LPASS_AUDIO_SWR_TX_CGCR 1
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#define LPASS_AUDIO_SWR_WSA_CGCR 2
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/* LPASS_AON_CC clocks */
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#define LPASS_AON_CC_PLL 0
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#define LPASS_AON_CC_PLL_OUT_EVEN 1
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#define LPASS_AON_CC_PLL_OUT_MAIN_CDIV_DIV_CLK_SRC 2
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#define LPASS_AON_CC_PLL_OUT_ODD 3
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#define LPASS_AON_CC_AUDIO_HM_H_CLK 4
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#define LPASS_AON_CC_CDIV_TX_MCLK_DIV_CLK_SRC 5
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#define LPASS_AON_CC_MAIN_RCG_CLK_SRC 6
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#define LPASS_AON_CC_TX_MCLK_2X_CLK 7
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#define LPASS_AON_CC_TX_MCLK_CLK 8
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#define LPASS_AON_CC_TX_MCLK_RCG_CLK_SRC 9
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#define LPASS_AON_CC_VA_MEM0_CLK 10
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/* LPASS_AON_CC power domains */
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#define LPASS_AON_CC_LPASS_AUDIO_HM_GDSC 0
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#endif
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