Greg Kroah-Hartman
598cf27219
Link: https://lore.kernel.org/r/20260217200002.683975158@linuxfoundation.org Tested-by: Florian Fainelli <florian.fainelli@broadcom.com> Tested-by: Takeshi Ogasawara <takeshi.ogasawara@futuring-girl.com> Tested-by: Peter Schneider <pschneider1968@googlemail.com> Tested-by: Jon Hunter <jonathanh@nvidia.com> Tested-by: Salvatore Bonaccorso <carnil@debian.org> Tested-by: Brett A C Sheffield <bacs@librecast.net> Tested-by: Mark Brown <broonie@kernel.org> Tested-by: Luna Jernberg <droidbittin@gmail.com> Tested-by: Ronald Warsow <rwarsow@gmx.de> Tested-by: Justin M. Forbes <jforbes@fedoraproject.org> Tested-by: Ron Economos <re@w6rz.net> Tested-by: Miguel Ojeda <ojeda@kernel.org> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
27 lines
783 B
C
27 lines
783 B
C
/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
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/*
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* Copyright (c) 2025 Collabora Ltd.
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* Author: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
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*/
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#ifndef _DT_BINDINGS_RESET_CONTROLLER_MT8196
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#define _DT_BINDINGS_RESET_CONTROLLER_MT8196
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/* PEXTP0 resets */
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#define MT8196_PEXTP0_RST0_PCIE0_MAC 0
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#define MT8196_PEXTP0_RST0_PCIE0_PHY 1
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/* PEXTP1 resets */
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#define MT8196_PEXTP1_RST0_PCIE1_MAC 0
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#define MT8196_PEXTP1_RST0_PCIE1_PHY 1
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#define MT8196_PEXTP1_RST0_PCIE2_MAC 2
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#define MT8196_PEXTP1_RST0_PCIE2_PHY 3
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/* UFS resets */
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#define MT8196_UFSAO_RST0_UFS_MPHY 0
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#define MT8196_UFSAO_RST1_UFS_UNIPRO 1
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#define MT8196_UFSAO_RST1_UFS_CRYPTO 2
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#define MT8196_UFSAO_RST1_UFSHCI 3
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#endif /* _DT_BINDINGS_RESET_CONTROLLER_MT8196 */
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