Greg Kroah-Hartman
598cf27219
Link: https://lore.kernel.org/r/20260217200002.683975158@linuxfoundation.org Tested-by: Florian Fainelli <florian.fainelli@broadcom.com> Tested-by: Takeshi Ogasawara <takeshi.ogasawara@futuring-girl.com> Tested-by: Peter Schneider <pschneider1968@googlemail.com> Tested-by: Jon Hunter <jonathanh@nvidia.com> Tested-by: Salvatore Bonaccorso <carnil@debian.org> Tested-by: Brett A C Sheffield <bacs@librecast.net> Tested-by: Mark Brown <broonie@kernel.org> Tested-by: Luna Jernberg <droidbittin@gmail.com> Tested-by: Ronald Warsow <rwarsow@gmx.de> Tested-by: Justin M. Forbes <jforbes@fedoraproject.org> Tested-by: Ron Economos <re@w6rz.net> Tested-by: Miguel Ojeda <ojeda@kernel.org> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
44 lines
1.1 KiB
C
44 lines
1.1 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Copyright (C) 2021, Google LLC.
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*/
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#include "apic.h"
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void apic_disable(void)
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{
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wrmsr(MSR_IA32_APICBASE,
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rdmsr(MSR_IA32_APICBASE) &
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~(MSR_IA32_APICBASE_ENABLE | MSR_IA32_APICBASE_EXTD));
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}
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void xapic_enable(void)
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{
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uint64_t val = rdmsr(MSR_IA32_APICBASE);
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/* Per SDM: to enable xAPIC when in x2APIC must first disable APIC */
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if (val & MSR_IA32_APICBASE_EXTD) {
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apic_disable();
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wrmsr(MSR_IA32_APICBASE,
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rdmsr(MSR_IA32_APICBASE) | MSR_IA32_APICBASE_ENABLE);
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} else if (!(val & MSR_IA32_APICBASE_ENABLE)) {
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wrmsr(MSR_IA32_APICBASE, val | MSR_IA32_APICBASE_ENABLE);
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}
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/*
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* Per SDM: reset value of spurious interrupt vector register has the
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* APIC software enabled bit=0. It must be enabled in addition to the
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* enable bit in the MSR.
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*/
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val = xapic_read_reg(APIC_SPIV) | APIC_SPIV_APIC_ENABLED;
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xapic_write_reg(APIC_SPIV, val);
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}
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void x2apic_enable(void)
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{
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wrmsr(MSR_IA32_APICBASE, rdmsr(MSR_IA32_APICBASE) |
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MSR_IA32_APICBASE_ENABLE | MSR_IA32_APICBASE_EXTD);
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x2apic_write_reg(APIC_SPIV,
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x2apic_read_reg(APIC_SPIV) | APIC_SPIV_APIC_ENABLED);
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}
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