Greg Kroah-Hartman
598cf27219
Link: https://lore.kernel.org/r/20260217200002.683975158@linuxfoundation.org Tested-by: Florian Fainelli <florian.fainelli@broadcom.com> Tested-by: Takeshi Ogasawara <takeshi.ogasawara@futuring-girl.com> Tested-by: Peter Schneider <pschneider1968@googlemail.com> Tested-by: Jon Hunter <jonathanh@nvidia.com> Tested-by: Salvatore Bonaccorso <carnil@debian.org> Tested-by: Brett A C Sheffield <bacs@librecast.net> Tested-by: Mark Brown <broonie@kernel.org> Tested-by: Luna Jernberg <droidbittin@gmail.com> Tested-by: Ronald Warsow <rwarsow@gmx.de> Tested-by: Justin M. Forbes <jforbes@fedoraproject.org> Tested-by: Ron Economos <re@w6rz.net> Tested-by: Miguel Ojeda <ojeda@kernel.org> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
33 lines
825 B
ArmAsm
33 lines
825 B
ArmAsm
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (C) 2014 Renesas Electronics Corporation
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*
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* Initialization of CNTVOFF register from secure mode
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*
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*/
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#include <linux/linkage.h>
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#include <asm/assembler.h>
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ENTRY(secure_cntvoff_init)
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.arch armv7-a
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/*
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* CNTVOFF has to be initialized either from non-secure Hypervisor
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* mode or secure Monitor mode with SCR.NS==1. If TrustZone is enabled
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* then it should be handled by the secure code. The CPU must implement
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* the virtualization extensions.
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*/
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cps #MON_MODE
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mrc p15, 0, r1, c1, c1, 0 /* Get Secure Config */
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orr r0, r1, #1
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mcr p15, 0, r0, c1, c1, 0 /* Set Non Secure bit */
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isb
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mov r0, #0
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mcrr p15, 4, r0, r0, c14 /* CNTVOFF = 0 */
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isb
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mcr p15, 0, r1, c1, c1, 0 /* Set Secure bit */
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isb
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cps #SVC_MODE
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ret lr
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ENDPROC(secure_cntvoff_init)
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