Greg Kroah-Hartman
598cf27219
Link: https://lore.kernel.org/r/20260217200002.683975158@linuxfoundation.org Tested-by: Florian Fainelli <florian.fainelli@broadcom.com> Tested-by: Takeshi Ogasawara <takeshi.ogasawara@futuring-girl.com> Tested-by: Peter Schneider <pschneider1968@googlemail.com> Tested-by: Jon Hunter <jonathanh@nvidia.com> Tested-by: Salvatore Bonaccorso <carnil@debian.org> Tested-by: Brett A C Sheffield <bacs@librecast.net> Tested-by: Mark Brown <broonie@kernel.org> Tested-by: Luna Jernberg <droidbittin@gmail.com> Tested-by: Ronald Warsow <rwarsow@gmx.de> Tested-by: Justin M. Forbes <jforbes@fedoraproject.org> Tested-by: Ron Economos <re@w6rz.net> Tested-by: Miguel Ojeda <ojeda@kernel.org> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
31 lines
892 B
C
31 lines
892 B
C
/* SPDX-License-Identifier: GPL-2.0-or-later */
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/*
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* Copyright (C) 2001 Mike Corrigan & Dave Engebretsen, IBM Corporation
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* Rewrite, cleanup:
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* Copyright (C) 2004 Olof Johansson <olof@lixom.net>, IBM Corporation
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*/
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#ifndef _ASM_POWERPC_TCE_H
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#define _ASM_POWERPC_TCE_H
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#ifdef __KERNEL__
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#include <asm/iommu.h>
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/*
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* Tces come in two formats, one for the virtual bus and a different
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* format for PCI. PCI TCEs can have hardware or software maintianed
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* coherency.
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*/
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#define TCE_VB 0
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#define TCE_PCI 1
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#define TCE_ENTRY_SIZE 8 /* each TCE is 64 bits */
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#define TCE_VALID 0x800 /* TCE valid */
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#define TCE_ALLIO 0x400 /* TCE valid for all lpars */
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#define TCE_PCI_WRITE 0x2 /* write from PCI allowed */
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#define TCE_PCI_READ 0x1 /* read from PCI allowed */
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#define TCE_VB_WRITE 0x1 /* write from VB allowed */
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#endif /* __KERNEL__ */
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#endif /* _ASM_POWERPC_TCE_H */
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