Greg Kroah-Hartman
598cf27219
Link: https://lore.kernel.org/r/20260217200002.683975158@linuxfoundation.org Tested-by: Florian Fainelli <florian.fainelli@broadcom.com> Tested-by: Takeshi Ogasawara <takeshi.ogasawara@futuring-girl.com> Tested-by: Peter Schneider <pschneider1968@googlemail.com> Tested-by: Jon Hunter <jonathanh@nvidia.com> Tested-by: Salvatore Bonaccorso <carnil@debian.org> Tested-by: Brett A C Sheffield <bacs@librecast.net> Tested-by: Mark Brown <broonie@kernel.org> Tested-by: Luna Jernberg <droidbittin@gmail.com> Tested-by: Ronald Warsow <rwarsow@gmx.de> Tested-by: Justin M. Forbes <jforbes@fedoraproject.org> Tested-by: Ron Economos <re@w6rz.net> Tested-by: Miguel Ojeda <ojeda@kernel.org> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
43 lines
937 B
YAML
43 lines
937 B
YAML
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/arm/calxeda/l2ecc.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Calxeda Highbank L2 cache ECC
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description: |
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Binding for the Calxeda Highbank L2 cache controller ECC device.
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This does not cover the actual L2 cache controller control registers,
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but just the error reporting functionality.
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maintainers:
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- Andre Przywara <andre.przywara@arm.com>
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properties:
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compatible:
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const: calxeda,hb-sregs-l2-ecc
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reg:
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maxItems: 1
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interrupts:
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items:
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- description: single bit error interrupt
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- description: double bit error interrupt
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required:
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- compatible
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- reg
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- interrupts
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additionalProperties: false
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examples:
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- |
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sregs@fff3c200 {
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compatible = "calxeda,hb-sregs-l2-ecc";
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reg = <0xfff3c200 0x100>;
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interrupts = <0 71 4>, <0 72 4>;
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};
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