Greg Kroah-Hartman
598cf27219
Link: https://lore.kernel.org/r/20260217200002.683975158@linuxfoundation.org Tested-by: Florian Fainelli <florian.fainelli@broadcom.com> Tested-by: Takeshi Ogasawara <takeshi.ogasawara@futuring-girl.com> Tested-by: Peter Schneider <pschneider1968@googlemail.com> Tested-by: Jon Hunter <jonathanh@nvidia.com> Tested-by: Salvatore Bonaccorso <carnil@debian.org> Tested-by: Brett A C Sheffield <bacs@librecast.net> Tested-by: Mark Brown <broonie@kernel.org> Tested-by: Luna Jernberg <droidbittin@gmail.com> Tested-by: Ronald Warsow <rwarsow@gmx.de> Tested-by: Justin M. Forbes <jforbes@fedoraproject.org> Tested-by: Ron Economos <re@w6rz.net> Tested-by: Miguel Ojeda <ojeda@kernel.org> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
62 lines
1.2 KiB
YAML
62 lines
1.2 KiB
YAML
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/clock/sophgo,sg2042-clkgen.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Sophgo SG2042 Clock Generator for divider/mux/gate
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maintainers:
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- Chen Wang <unicorn_wang@outlook.com>
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properties:
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compatible:
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const: sophgo,sg2042-clkgen
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reg:
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maxItems: 1
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clocks:
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items:
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- description: Main PLL
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- description: Fixed PLL
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- description: DDR PLL 0
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- description: DDR PLL 1
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clock-names:
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items:
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- const: mpll
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- const: fpll
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- const: dpll0
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- const: dpll1
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'#clock-cells':
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const: 1
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description:
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See <dt-bindings/clock/sophgo,sg2042-clkgen.h> for valid indices.
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required:
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- compatible
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- reg
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- clocks
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- clock-names
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- '#clock-cells'
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additionalProperties: false
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examples:
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- |
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clock-controller@30012000 {
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compatible = "sophgo,sg2042-clkgen";
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reg = <0x30012000 0x1000>;
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clocks = <&pllclk 0>,
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<&pllclk 1>,
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<&pllclk 2>,
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<&pllclk 3>;
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clock-names = "mpll",
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"fpll",
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"dpll0",
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"dpll1";
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#clock-cells = <1>;
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};
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