Greg Kroah-Hartman
598cf27219
Link: https://lore.kernel.org/r/20260217200002.683975158@linuxfoundation.org Tested-by: Florian Fainelli <florian.fainelli@broadcom.com> Tested-by: Takeshi Ogasawara <takeshi.ogasawara@futuring-girl.com> Tested-by: Peter Schneider <pschneider1968@googlemail.com> Tested-by: Jon Hunter <jonathanh@nvidia.com> Tested-by: Salvatore Bonaccorso <carnil@debian.org> Tested-by: Brett A C Sheffield <bacs@librecast.net> Tested-by: Mark Brown <broonie@kernel.org> Tested-by: Luna Jernberg <droidbittin@gmail.com> Tested-by: Ronald Warsow <rwarsow@gmx.de> Tested-by: Justin M. Forbes <jforbes@fedoraproject.org> Tested-by: Ron Economos <re@w6rz.net> Tested-by: Miguel Ojeda <ojeda@kernel.org> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
40 lines
1.3 KiB
Plaintext
40 lines
1.3 KiB
Plaintext
Binding for Texas Instruments ADPLL clock.
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This binding uses the common clock binding[1]. It assumes a
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register-mapped ADPLL with two to three selectable input clocks
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and three to four children.
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[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
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Required properties:
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- compatible : shall be one of "ti,dm814-adpll-s-clock" or
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"ti,dm814-adpll-lj-clock" depending on the type of the ADPLL
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- #clock-cells : from common clock binding; shall be set to 1.
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- clocks : link phandles of parent clocks clkinp and clkinpulow, note
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that the adpll-s-clock also has an optional clkinphif
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- reg : address and length of the register set for controlling the ADPLL.
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Examples:
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adpll_mpu_ck: adpll@40 {
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#clock-cells = <1>;
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compatible = "ti,dm814-adpll-s-clock";
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reg = <0x40 0x40>;
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clocks = <&devosc_ck &devosc_ck &devosc_ck>;
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clock-names = "clkinp", "clkinpulow", "clkinphif";
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clock-output-names = "481c5040.adpll.dcoclkldo",
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"481c5040.adpll.clkout",
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"481c5040.adpll.clkoutx2",
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"481c5040.adpll.clkouthif";
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};
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adpll_dsp_ck: adpll@80 {
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#clock-cells = <1>;
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compatible = "ti,dm814-adpll-lj-clock";
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reg = <0x80 0x30>;
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clocks = <&devosc_ck &devosc_ck>;
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clock-names = "clkinp", "clkinpulow";
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clock-output-names = "481c5080.adpll.dcoclkldo",
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"481c5080.adpll.clkout",
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"481c5080.adpll.clkoutldo";
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};
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