Greg Kroah-Hartman
598cf27219
Link: https://lore.kernel.org/r/20260217200002.683975158@linuxfoundation.org Tested-by: Florian Fainelli <florian.fainelli@broadcom.com> Tested-by: Takeshi Ogasawara <takeshi.ogasawara@futuring-girl.com> Tested-by: Peter Schneider <pschneider1968@googlemail.com> Tested-by: Jon Hunter <jonathanh@nvidia.com> Tested-by: Salvatore Bonaccorso <carnil@debian.org> Tested-by: Brett A C Sheffield <bacs@librecast.net> Tested-by: Mark Brown <broonie@kernel.org> Tested-by: Luna Jernberg <droidbittin@gmail.com> Tested-by: Ronald Warsow <rwarsow@gmx.de> Tested-by: Justin M. Forbes <jforbes@fedoraproject.org> Tested-by: Ron Economos <re@w6rz.net> Tested-by: Miguel Ojeda <ojeda@kernel.org> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
60 lines
1.3 KiB
YAML
60 lines
1.3 KiB
YAML
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/clock/xlnx,vcu.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: LogicoreIP designed compatible with Xilinx ZYNQ family.
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maintainers:
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- Rohit Visavalia <rohit.visavalia@amd.com>
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description:
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LogicoreIP design to provide the isolation between processing system
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and programmable logic. Also provides the list of register set to configure
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the frequency.
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properties:
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compatible:
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items:
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- enum:
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- xlnx,vcu
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- xlnx,vcu-logicoreip-1.0
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reg:
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maxItems: 1
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clocks:
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items:
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- description: pll ref clocksource
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- description: aclk
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clock-names:
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items:
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- const: pll_ref
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- const: aclk
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reset-gpios:
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maxItems: 1
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required:
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- reg
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- clocks
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- clock-names
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additionalProperties: false
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examples:
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- |
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#include <dt-bindings/gpio/gpio.h>
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fpga {
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#address-cells = <2>;
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#size-cells = <2>;
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xlnx_vcu: vcu@a0040000 {
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compatible = "xlnx,vcu-logicoreip-1.0";
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reg = <0x0 0xa0040000 0x0 0x1000>;
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reset-gpios = <&gpio 78 GPIO_ACTIVE_HIGH>;
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clocks = <&si570_1>, <&clkc 71>;
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clock-names = "pll_ref", "aclk";
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};
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};
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