Greg Kroah-Hartman
598cf27219
Link: https://lore.kernel.org/r/20260217200002.683975158@linuxfoundation.org Tested-by: Florian Fainelli <florian.fainelli@broadcom.com> Tested-by: Takeshi Ogasawara <takeshi.ogasawara@futuring-girl.com> Tested-by: Peter Schneider <pschneider1968@googlemail.com> Tested-by: Jon Hunter <jonathanh@nvidia.com> Tested-by: Salvatore Bonaccorso <carnil@debian.org> Tested-by: Brett A C Sheffield <bacs@librecast.net> Tested-by: Mark Brown <broonie@kernel.org> Tested-by: Luna Jernberg <droidbittin@gmail.com> Tested-by: Ronald Warsow <rwarsow@gmx.de> Tested-by: Justin M. Forbes <jforbes@fedoraproject.org> Tested-by: Ron Economos <re@w6rz.net> Tested-by: Miguel Ojeda <ojeda@kernel.org> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
41 lines
1.1 KiB
Plaintext
41 lines
1.1 KiB
Plaintext
Tegra124 CPU frequency scaling driver bindings
|
|
----------------------------------------------
|
|
|
|
Both required and optional properties listed below must be defined
|
|
under node /cpus/cpu@0.
|
|
|
|
Required properties:
|
|
- clocks: Must contain an entry for each entry in clock-names.
|
|
See ../clocks/clock-bindings.txt for details.
|
|
- clock-names: Must include the following entries:
|
|
- cpu_g: Clock mux for the fast CPU cluster.
|
|
- pll_x: Fast PLL clocksource.
|
|
- pll_p: Auxiliary PLL used during fast PLL rate changes.
|
|
- dfll: Fast DFLL clocksource that also automatically scales CPU voltage.
|
|
|
|
Optional properties:
|
|
- clock-latency: Specify the possible maximum transition latency for clock,
|
|
in unit of nanoseconds.
|
|
|
|
Example:
|
|
--------
|
|
cpus {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
cpu@0 {
|
|
device_type = "cpu";
|
|
compatible = "arm,cortex-a15";
|
|
reg = <0>;
|
|
|
|
clocks = <&tegra_car TEGRA124_CLK_CCLK_G>,
|
|
<&tegra_car TEGRA124_CLK_PLL_X>,
|
|
<&tegra_car TEGRA124_CLK_PLL_P>,
|
|
<&dfll>;
|
|
clock-names = "cpu_g", "pll_x", "pll_p", "dfll";
|
|
clock-latency = <300000>;
|
|
};
|
|
|
|
<...>
|
|
};
|