Link: https://lore.kernel.org/r/20260217200002.683975158@linuxfoundation.org Tested-by: Florian Fainelli <florian.fainelli@broadcom.com> Tested-by: Takeshi Ogasawara <takeshi.ogasawara@futuring-girl.com> Tested-by: Peter Schneider <pschneider1968@googlemail.com> Tested-by: Jon Hunter <jonathanh@nvidia.com> Tested-by: Salvatore Bonaccorso <carnil@debian.org> Tested-by: Brett A C Sheffield <bacs@librecast.net> Tested-by: Mark Brown <broonie@kernel.org> Tested-by: Luna Jernberg <droidbittin@gmail.com> Tested-by: Ronald Warsow <rwarsow@gmx.de> Tested-by: Justin M. Forbes <jforbes@fedoraproject.org> Tested-by: Ron Economos <re@w6rz.net> Tested-by: Miguel Ojeda <ojeda@kernel.org> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
36 lines
900 B
Plaintext
36 lines
900 B
Plaintext
ARC PGU
|
|
|
|
This is a display controller found on several development boards produced
|
|
by Synopsys. The ARC PGU is an RGB streamer that reads the data from a
|
|
framebuffer and sends it to a single digital encoder (usually HDMI).
|
|
|
|
Required properties:
|
|
- compatible: "snps,arcpgu"
|
|
- reg: Physical base address and length of the controller's registers.
|
|
- clocks: A list of phandle + clock-specifier pairs, one for each
|
|
entry in 'clock-names'.
|
|
- clock-names: A list of clock names. For ARC PGU it should contain:
|
|
- "pxlclk" for the clock feeding the output PLL of the controller.
|
|
|
|
Required sub-nodes:
|
|
- port: The PGU connection to an encoder chip.
|
|
|
|
Example:
|
|
|
|
/ {
|
|
...
|
|
|
|
pgu@XXXXXXXX {
|
|
compatible = "snps,arcpgu";
|
|
reg = <0xXXXXXXXX 0x400>;
|
|
clocks = <&clock_node>;
|
|
clock-names = "pxlclk";
|
|
|
|
port {
|
|
pgu_output: endpoint {
|
|
remote-endpoint = <&hdmi_enc_input>;
|
|
};
|
|
};
|
|
};
|
|
};
|