Greg Kroah-Hartman
598cf27219
Link: https://lore.kernel.org/r/20260217200002.683975158@linuxfoundation.org Tested-by: Florian Fainelli <florian.fainelli@broadcom.com> Tested-by: Takeshi Ogasawara <takeshi.ogasawara@futuring-girl.com> Tested-by: Peter Schneider <pschneider1968@googlemail.com> Tested-by: Jon Hunter <jonathanh@nvidia.com> Tested-by: Salvatore Bonaccorso <carnil@debian.org> Tested-by: Brett A C Sheffield <bacs@librecast.net> Tested-by: Mark Brown <broonie@kernel.org> Tested-by: Luna Jernberg <droidbittin@gmail.com> Tested-by: Ronald Warsow <rwarsow@gmx.de> Tested-by: Justin M. Forbes <jforbes@fedoraproject.org> Tested-by: Ron Economos <re@w6rz.net> Tested-by: Miguel Ojeda <ojeda@kernel.org> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
136 lines
3.2 KiB
YAML
136 lines
3.2 KiB
YAML
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/iio/adc/renesas,r9a09g077-adc.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Renesas RZ/T2H / RZ/N2H ADC12
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maintainers:
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- Cosmin Tanislav <cosmin-gabriel.tanislav.xa@renesas.com>
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description: |
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A/D Converter block is a successive approximation analog-to-digital converter
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with a 12-bit accuracy. Up to 16 analog input channels can be selected.
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Conversions can be performed in single or continuous mode. Result of the ADC
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is stored in a 16-bit data register corresponding to each channel.
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properties:
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compatible:
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oneOf:
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- items:
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- const: renesas,r9a09g087-adc # RZ/N2H
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- const: renesas,r9a09g077-adc # RZ/T2H
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- items:
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- const: renesas,r9a09g077-adc # RZ/T2H
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reg:
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maxItems: 1
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interrupts:
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items:
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- description: A/D scan end interrupt
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- description: A/D scan end interrupt for Group B
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- description: A/D scan end interrupt for Group C
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- description: Window A compare match
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- description: Window B compare match
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- description: Compare match
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- description: Compare mismatch
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interrupt-names:
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items:
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- const: adi
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- const: gbadi
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- const: gcadi
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- const: cmpai
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- const: cmpbi
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- const: wcmpm
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- const: wcmpum
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clocks:
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items:
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- description: Converter clock
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- description: Peripheral clock
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clock-names:
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items:
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- const: adclk
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- const: pclk
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power-domains:
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maxItems: 1
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'#address-cells':
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const: 1
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'#size-cells':
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const: 0
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"#io-channel-cells":
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const: 1
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patternProperties:
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"^channel@[0-9a-f]$":
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$ref: adc.yaml
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type: object
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description: The external channels which are connected to the ADC.
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properties:
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reg:
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description: The channel number.
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maximum: 15
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required:
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- reg
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additionalProperties: false
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required:
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- compatible
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- reg
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- interrupts
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- clocks
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- clock-names
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- power-domains
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additionalProperties: false
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examples:
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- |
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#include <dt-bindings/clock/renesas,r9a09g077-cpg-mssr.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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adc@80008000 {
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compatible = "renesas,r9a09g077-adc";
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reg = <0x80008000 0x400>;
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interrupts = <GIC_SPI 708 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 709 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 710 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 711 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 712 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 855 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 856 IRQ_TYPE_EDGE_RISING>;
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interrupt-names = "adi", "gbadi", "gcadi",
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"cmpai", "cmpbi", "wcmpm", "wcmpum";
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clocks = <&cpg CPG_CORE R9A09G077_CLK_PCLKL>,
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<&cpg CPG_MOD 225>;
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clock-names = "adclk", "pclk";
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power-domains = <&cpg>;
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#address-cells = <1>;
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#size-cells = <0>;
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#io-channel-cells = <1>;
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channel@0 {
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reg = <0x0>;
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};
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channel@1 {
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reg = <0x1>;
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};
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channel@2 {
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reg = <0x2>;
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};
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channel@3 {
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reg = <0x3>;
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};
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};
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