Greg Kroah-Hartman
598cf27219
Link: https://lore.kernel.org/r/20260217200002.683975158@linuxfoundation.org Tested-by: Florian Fainelli <florian.fainelli@broadcom.com> Tested-by: Takeshi Ogasawara <takeshi.ogasawara@futuring-girl.com> Tested-by: Peter Schneider <pschneider1968@googlemail.com> Tested-by: Jon Hunter <jonathanh@nvidia.com> Tested-by: Salvatore Bonaccorso <carnil@debian.org> Tested-by: Brett A C Sheffield <bacs@librecast.net> Tested-by: Mark Brown <broonie@kernel.org> Tested-by: Luna Jernberg <droidbittin@gmail.com> Tested-by: Ronald Warsow <rwarsow@gmx.de> Tested-by: Justin M. Forbes <jforbes@fedoraproject.org> Tested-by: Ron Economos <re@w6rz.net> Tested-by: Miguel Ojeda <ojeda@kernel.org> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
72 lines
1.3 KiB
YAML
72 lines
1.3 KiB
YAML
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/net/mscc,miim.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Microsemi MII Management Controller (MIIM)
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maintainers:
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- Alexandre Belloni <alexandre.belloni@bootlin.com>
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allOf:
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- $ref: mdio.yaml#
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properties:
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compatible:
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enum:
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- mscc,ocelot-miim
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- microchip,lan966x-miim
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"#address-cells":
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const: 1
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"#size-cells":
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const: 0
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reg:
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items:
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- description: base address
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- description: associated reset register for internal PHYs
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minItems: 1
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interrupts:
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maxItems: 1
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clocks:
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maxItems: 1
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clock-frequency: true
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resets:
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items:
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- description:
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Reset shared with all blocks attached to the Switch Core Register
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Bus (CSR) including VRAP slave.
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reset-names:
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items:
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- const: switch
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required:
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- compatible
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- reg
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- "#address-cells"
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- "#size-cells"
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unevaluatedProperties: false
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examples:
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- |
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mdio@107009c {
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compatible = "mscc,ocelot-miim";
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reg = <0x107009c 0x36>, <0x10700f0 0x8>;
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interrupts = <14>;
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#address-cells = <1>;
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#size-cells = <0>;
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phy0: ethernet-phy@0 {
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reg = <0>;
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};
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};
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