Greg Kroah-Hartman
598cf27219
Link: https://lore.kernel.org/r/20260217200002.683975158@linuxfoundation.org Tested-by: Florian Fainelli <florian.fainelli@broadcom.com> Tested-by: Takeshi Ogasawara <takeshi.ogasawara@futuring-girl.com> Tested-by: Peter Schneider <pschneider1968@googlemail.com> Tested-by: Jon Hunter <jonathanh@nvidia.com> Tested-by: Salvatore Bonaccorso <carnil@debian.org> Tested-by: Brett A C Sheffield <bacs@librecast.net> Tested-by: Mark Brown <broonie@kernel.org> Tested-by: Luna Jernberg <droidbittin@gmail.com> Tested-by: Ronald Warsow <rwarsow@gmx.de> Tested-by: Justin M. Forbes <jforbes@fedoraproject.org> Tested-by: Ron Economos <re@w6rz.net> Tested-by: Miguel Ojeda <ojeda@kernel.org> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
110 lines
2.2 KiB
YAML
110 lines
2.2 KiB
YAML
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/phy/qcom,ipq5332-uniphy-pcie-phy.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Qualcomm UNIPHY PCIe 28LP PHY
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maintainers:
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- Nitheesh Sekar <quic_nsekar@quicinc.com>
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- Varadarajan Narayanan <quic_varada@quicinc.com>
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description:
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PCIe and USB combo PHY found in Qualcomm IPQ5018 & IPQ5332 SoCs
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properties:
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compatible:
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enum:
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- qcom,ipq5018-uniphy-pcie-phy
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- qcom,ipq5332-uniphy-pcie-phy
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reg:
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maxItems: 1
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clocks:
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minItems: 1
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maxItems: 2
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resets:
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minItems: 2
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maxItems: 3
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"#phy-cells":
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const: 0
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"#clock-cells":
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const: 0
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num-lanes:
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$ref: /schemas/types.yaml#/definitions/uint32
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enum: [1, 2]
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required:
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- compatible
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- reg
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- clocks
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- resets
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- "#phy-cells"
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- "#clock-cells"
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- num-lanes
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additionalProperties: false
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allOf:
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- if:
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properties:
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compatible:
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contains:
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enum:
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- qcom,ipq5018-uniphy-pcie-phy
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then:
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properties:
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clocks:
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items:
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- description: pcie pipe clock
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resets:
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items:
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- description: phy reset
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- description: cfg reset
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- if:
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properties:
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compatible:
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contains:
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enum:
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- qcom,ipq5332-uniphy-pcie-phy
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then:
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properties:
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clocks:
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items:
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- description: pcie pipe clock
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- description: pcie ahb clock
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resets:
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items:
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- description: phy reset
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- description: ahb reset
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- description: cfg reset
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examples:
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- |
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#include <dt-bindings/clock/qcom,ipq5332-gcc.h>
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pcie0_phy: phy@4b0000 {
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compatible = "qcom,ipq5332-uniphy-pcie-phy";
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reg = <0x004b0000 0x800>;
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clocks = <&gcc GCC_PCIE3X1_0_PIPE_CLK>,
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<&gcc GCC_PCIE3X1_PHY_AHB_CLK>;
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resets = <&gcc GCC_PCIE3X1_0_PHY_BCR>,
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<&gcc GCC_PCIE3X1_PHY_AHB_CLK_ARES>,
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<&gcc GCC_PCIE3X1_0_PHY_PHY_BCR>;
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#clock-cells = <0>;
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#phy-cells = <0>;
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num-lanes = <1>;
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};
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