Greg Kroah-Hartman
598cf27219
Link: https://lore.kernel.org/r/20260217200002.683975158@linuxfoundation.org Tested-by: Florian Fainelli <florian.fainelli@broadcom.com> Tested-by: Takeshi Ogasawara <takeshi.ogasawara@futuring-girl.com> Tested-by: Peter Schneider <pschneider1968@googlemail.com> Tested-by: Jon Hunter <jonathanh@nvidia.com> Tested-by: Salvatore Bonaccorso <carnil@debian.org> Tested-by: Brett A C Sheffield <bacs@librecast.net> Tested-by: Mark Brown <broonie@kernel.org> Tested-by: Luna Jernberg <droidbittin@gmail.com> Tested-by: Ronald Warsow <rwarsow@gmx.de> Tested-by: Justin M. Forbes <jforbes@fedoraproject.org> Tested-by: Ron Economos <re@w6rz.net> Tested-by: Miguel Ojeda <ojeda@kernel.org> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
87 lines
1.6 KiB
YAML
87 lines
1.6 KiB
YAML
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/phy/qcom,pcie2-phy.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Qualcomm PCIe2 PHY controller
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maintainers:
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- Vinod Koul <vkoul@kernel.org>
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description:
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The Qualcomm PCIe2 PHY is a Synopsys based phy found in a number of Qualcomm
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platforms.
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properties:
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compatible:
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items:
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- const: qcom,qcs404-pcie2-phy
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- const: qcom,pcie2-phy
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reg:
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items:
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- description: PHY register set
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clocks:
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items:
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- description: a clock-specifier pair for the "pipe" clock
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clock-output-names:
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maxItems: 1
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"#clock-cells":
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const: 0
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"#phy-cells":
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const: 0
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vdda-vp-supply:
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description: low voltage regulator
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vdda-vph-supply:
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description: high voltage regulator
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resets:
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maxItems: 2
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reset-names:
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items:
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- const: phy
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- const: pipe
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required:
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- compatible
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- reg
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- clocks
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- clock-output-names
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- "#clock-cells"
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- "#phy-cells"
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- vdda-vp-supply
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- vdda-vph-supply
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- resets
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- reset-names
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additionalProperties: false
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examples:
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- |
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#include <dt-bindings/clock/qcom,gcc-qcs404.h>
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phy@7786000 {
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compatible = "qcom,qcs404-pcie2-phy", "qcom,pcie2-phy";
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reg = <0x07786000 0xb8>;
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clocks = <&gcc GCC_PCIE_0_PIPE_CLK>;
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resets = <&gcc GCC_PCIEPHY_0_PHY_BCR>,
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<&gcc GCC_PCIE_0_PIPE_ARES>;
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reset-names = "phy", "pipe";
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vdda-vp-supply = <&vreg_l3_1p05>;
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vdda-vph-supply = <&vreg_l5_1p8>;
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clock-output-names = "pcie_0_pipe_clk";
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#clock-cells = <0>;
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#phy-cells = <0>;
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};
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...
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