Greg Kroah-Hartman
598cf27219
Link: https://lore.kernel.org/r/20260217200002.683975158@linuxfoundation.org Tested-by: Florian Fainelli <florian.fainelli@broadcom.com> Tested-by: Takeshi Ogasawara <takeshi.ogasawara@futuring-girl.com> Tested-by: Peter Schneider <pschneider1968@googlemail.com> Tested-by: Jon Hunter <jonathanh@nvidia.com> Tested-by: Salvatore Bonaccorso <carnil@debian.org> Tested-by: Brett A C Sheffield <bacs@librecast.net> Tested-by: Mark Brown <broonie@kernel.org> Tested-by: Luna Jernberg <droidbittin@gmail.com> Tested-by: Ronald Warsow <rwarsow@gmx.de> Tested-by: Justin M. Forbes <jforbes@fedoraproject.org> Tested-by: Ron Economos <re@w6rz.net> Tested-by: Miguel Ojeda <ojeda@kernel.org> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
118 lines
2.9 KiB
YAML
118 lines
2.9 KiB
YAML
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/power/mediatek,mt8196-gpufreq.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: MediaTek MFlexGraphics Power and Frequency Controller
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maintainers:
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- Nicolas Frattaroli <nicolas.frattaroli@collabora.com>
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description:
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A special-purpose embedded MCU to control power and frequency of GPU devices
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using MediaTek Flexible Graphics integration hardware.
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properties:
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$nodename:
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pattern: '^power-controller@[a-f0-9]+$'
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compatible:
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enum:
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- mediatek,mt8196-gpufreq
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reg:
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items:
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- description: GPR memory area
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- description: RPC memory area
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- description: SoC variant ID register
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reg-names:
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items:
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- const: gpr
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- const: rpc
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- const: hw-revision
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clocks:
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items:
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- description: main clock of the embedded controller (EB)
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- description: core PLL
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- description: stack 0 PLL
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- description: stack 1 PLL
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clock-names:
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items:
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- const: eb
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- const: core
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- const: stack0
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- const: stack1
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mboxes:
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items:
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- description: FastDVFS events
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- description: frequency control
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- description: sleep control
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- description: timer control
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- description: frequency hopping control
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- description: hardware voter control
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- description: FastDVFS control
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mbox-names:
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items:
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- const: fast-dvfs-event
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- const: gpufreq
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- const: sleep
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- const: timer
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- const: fhctl
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- const: ccf
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- const: fast-dvfs
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memory-region:
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items:
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- description: phandle to the GPUEB shared memory
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"#clock-cells":
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const: 1
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"#power-domain-cells":
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const: 0
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required:
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- compatible
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- reg
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- reg-names
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- clocks
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- clock-names
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- mboxes
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- mbox-names
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- memory-region
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- "#clock-cells"
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- "#power-domain-cells"
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additionalProperties: false
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examples:
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- |
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#include <dt-bindings/clock/mediatek,mt8196-clock.h>
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power-controller@4b09fd00 {
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compatible = "mediatek,mt8196-gpufreq";
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reg = <0x4b09fd00 0x80>,
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<0x4b800000 0x1000>,
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<0x4b860128 0x4>;
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reg-names = "gpr", "rpc", "hw-revision";
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clocks = <&topckgen CLK_TOP_MFG_EB>,
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<&mfgpll CLK_MFG_AO_MFGPLL>,
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<&mfgpll_sc0 CLK_MFGSC0_AO_MFGPLL_SC0>,
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<&mfgpll_sc1 CLK_MFGSC1_AO_MFGPLL_SC1>;
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clock-names = "eb", "core", "stack0", "stack1";
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mboxes = <&gpueb_mbox 0>, <&gpueb_mbox 1>, <&gpueb_mbox 2>,
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<&gpueb_mbox 3>, <&gpueb_mbox 4>, <&gpueb_mbox 5>,
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<&gpueb_mbox 7>;
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mbox-names = "fast-dvfs-event", "gpufreq", "sleep", "timer", "fhctl",
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"ccf", "fast-dvfs";
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memory-region = <&gpueb_shared_memory>;
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#clock-cells = <1>;
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#power-domain-cells = <0>;
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};
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