Greg Kroah-Hartman
598cf27219
Link: https://lore.kernel.org/r/20260217200002.683975158@linuxfoundation.org Tested-by: Florian Fainelli <florian.fainelli@broadcom.com> Tested-by: Takeshi Ogasawara <takeshi.ogasawara@futuring-girl.com> Tested-by: Peter Schneider <pschneider1968@googlemail.com> Tested-by: Jon Hunter <jonathanh@nvidia.com> Tested-by: Salvatore Bonaccorso <carnil@debian.org> Tested-by: Brett A C Sheffield <bacs@librecast.net> Tested-by: Mark Brown <broonie@kernel.org> Tested-by: Luna Jernberg <droidbittin@gmail.com> Tested-by: Ronald Warsow <rwarsow@gmx.de> Tested-by: Justin M. Forbes <jforbes@fedoraproject.org> Tested-by: Ron Economos <re@w6rz.net> Tested-by: Miguel Ojeda <ojeda@kernel.org> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
20 lines
472 B
Plaintext
20 lines
472 B
Plaintext
Microsemi Ocelot reset controller
|
|
|
|
The DEVCPU_GCB:CHIP_REGS have a SOFT_RST register that can be used to reset the
|
|
SoC core.
|
|
|
|
The reset registers are both present in the MSCC vcoreiii MIPS and
|
|
microchip Sparx5 armv8 SoC's.
|
|
|
|
Required Properties:
|
|
|
|
- compatible: "mscc,ocelot-chip-reset", "mscc,luton-chip-reset",
|
|
"mscc,jaguar2-chip-reset" or "microchip,sparx5-chip-reset"
|
|
|
|
Example:
|
|
reset@1070008 {
|
|
compatible = "mscc,ocelot-chip-reset";
|
|
reg = <0x1070008 0x4>;
|
|
};
|
|
|