Greg Kroah-Hartman
598cf27219
Link: https://lore.kernel.org/r/20260217200002.683975158@linuxfoundation.org Tested-by: Florian Fainelli <florian.fainelli@broadcom.com> Tested-by: Takeshi Ogasawara <takeshi.ogasawara@futuring-girl.com> Tested-by: Peter Schneider <pschneider1968@googlemail.com> Tested-by: Jon Hunter <jonathanh@nvidia.com> Tested-by: Salvatore Bonaccorso <carnil@debian.org> Tested-by: Brett A C Sheffield <bacs@librecast.net> Tested-by: Mark Brown <broonie@kernel.org> Tested-by: Luna Jernberg <droidbittin@gmail.com> Tested-by: Ronald Warsow <rwarsow@gmx.de> Tested-by: Justin M. Forbes <jforbes@fedoraproject.org> Tested-by: Ron Economos <re@w6rz.net> Tested-by: Miguel Ojeda <ojeda@kernel.org> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
90 lines
2.0 KiB
YAML
90 lines
2.0 KiB
YAML
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/spi/qcom,spi-qpic-snand.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Qualcomm QPIC NAND controller
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maintainers:
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- Md sadre Alam <quic_mdalam@quicinc.com>
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description:
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The QCOM QPIC-SPI-NAND flash controller is an extended version of
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the QCOM QPIC NAND flash controller. It can work both in serial
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and parallel mode. It supports typical SPI-NAND page cache
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operations in single, dual or quad IO mode with pipelined ECC
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encoding/decoding using the QPIC ECC HW engine.
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allOf:
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- $ref: /schemas/spi/spi-controller.yaml#
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properties:
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compatible:
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oneOf:
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- items:
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- enum:
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- qcom,ipq5018-snand
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- qcom,ipq5332-snand
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- qcom,ipq5424-snand
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- const: qcom,ipq9574-snand
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- const: qcom,ipq9574-snand
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reg:
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maxItems: 1
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clocks:
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maxItems: 3
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clock-names:
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items:
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- const: core
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- const: aon
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- const: iom
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dmas:
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items:
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- description: tx DMA channel
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- description: rx DMA channel
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- description: cmd DMA channel
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dma-names:
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items:
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- const: tx
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- const: rx
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- const: cmd
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required:
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- compatible
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- reg
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- clocks
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- clock-names
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unevaluatedProperties: false
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examples:
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- |
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#include <dt-bindings/clock/qcom,ipq9574-gcc.h>
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spi@79b0000 {
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compatible = "qcom,ipq9574-snand";
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reg = <0x1ac00000 0x800>;
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clocks = <&gcc GCC_QPIC_CLK>,
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<&gcc GCC_QPIC_AHB_CLK>,
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<&gcc GCC_QPIC_IO_MACRO_CLK>;
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clock-names = "core", "aon", "iom";
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#address-cells = <1>;
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#size-cells = <0>;
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flash@0 {
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compatible = "spi-nand";
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reg = <0>;
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#address-cells = <1>;
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#size-cells = <1>;
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nand-ecc-engine = <&qpic_nand>;
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nand-ecc-strength = <4>;
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nand-ecc-step-size = <512>;
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};
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};
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