Greg Kroah-Hartman
598cf27219
Link: https://lore.kernel.org/r/20260217200002.683975158@linuxfoundation.org Tested-by: Florian Fainelli <florian.fainelli@broadcom.com> Tested-by: Takeshi Ogasawara <takeshi.ogasawara@futuring-girl.com> Tested-by: Peter Schneider <pschneider1968@googlemail.com> Tested-by: Jon Hunter <jonathanh@nvidia.com> Tested-by: Salvatore Bonaccorso <carnil@debian.org> Tested-by: Brett A C Sheffield <bacs@librecast.net> Tested-by: Mark Brown <broonie@kernel.org> Tested-by: Luna Jernberg <droidbittin@gmail.com> Tested-by: Ronald Warsow <rwarsow@gmx.de> Tested-by: Justin M. Forbes <jforbes@fedoraproject.org> Tested-by: Ron Economos <re@w6rz.net> Tested-by: Miguel Ojeda <ojeda@kernel.org> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
82 lines
1.4 KiB
YAML
82 lines
1.4 KiB
YAML
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
|
%YAML 1.2
|
|
---
|
|
$id: http://devicetree.org/schemas/spi/spi-zynqmp-qspi.yaml#
|
|
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
|
|
|
title: Xilinx Zynq UltraScale+ MPSoC GQSPI controller
|
|
|
|
maintainers:
|
|
- Michal Simek <michal.simek@amd.com>
|
|
|
|
properties:
|
|
compatible:
|
|
enum:
|
|
- xlnx,versal-qspi-1.0
|
|
- xlnx,zynqmp-qspi-1.0
|
|
|
|
reg:
|
|
minItems: 1
|
|
maxItems: 2
|
|
|
|
interrupts:
|
|
maxItems: 1
|
|
|
|
clock-names:
|
|
items:
|
|
- const: ref_clk
|
|
- const: pclk
|
|
|
|
clocks:
|
|
maxItems: 2
|
|
|
|
iommus:
|
|
maxItems: 1
|
|
|
|
power-domains:
|
|
maxItems: 1
|
|
|
|
required:
|
|
- compatible
|
|
- reg
|
|
- interrupts
|
|
- clock-names
|
|
- clocks
|
|
|
|
unevaluatedProperties: false
|
|
|
|
allOf:
|
|
- $ref: spi-controller.yaml#
|
|
|
|
- if:
|
|
properties:
|
|
compatible:
|
|
contains:
|
|
const: xlnx,zynqmp-qspi-1.0
|
|
then:
|
|
properties:
|
|
reg:
|
|
minItems: 2
|
|
|
|
else:
|
|
properties:
|
|
reg:
|
|
maxItems: 1
|
|
|
|
examples:
|
|
- |
|
|
soc {
|
|
#address-cells = <2>;
|
|
#size-cells = <2>;
|
|
|
|
qspi: spi@ff0f0000 {
|
|
compatible = "xlnx,zynqmp-qspi-1.0";
|
|
clocks = <&zynqmp_clk 53>, <&zynqmp_clk 82>;
|
|
clock-names = "ref_clk", "pclk";
|
|
interrupts = <0 15 4>;
|
|
interrupt-parent = <&gic>;
|
|
reg = <0x0 0xff0f0000 0x0 0x1000>,
|
|
<0x0 0xc0000000 0x0 0x8000000>;
|
|
};
|
|
};
|