Greg Kroah-Hartman
598cf27219
Link: https://lore.kernel.org/r/20260217200002.683975158@linuxfoundation.org Tested-by: Florian Fainelli <florian.fainelli@broadcom.com> Tested-by: Takeshi Ogasawara <takeshi.ogasawara@futuring-girl.com> Tested-by: Peter Schneider <pschneider1968@googlemail.com> Tested-by: Jon Hunter <jonathanh@nvidia.com> Tested-by: Salvatore Bonaccorso <carnil@debian.org> Tested-by: Brett A C Sheffield <bacs@librecast.net> Tested-by: Mark Brown <broonie@kernel.org> Tested-by: Luna Jernberg <droidbittin@gmail.com> Tested-by: Ronald Warsow <rwarsow@gmx.de> Tested-by: Justin M. Forbes <jforbes@fedoraproject.org> Tested-by: Ron Economos <re@w6rz.net> Tested-by: Miguel Ojeda <ojeda@kernel.org> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
88 lines
1.5 KiB
Devicetree
88 lines
1.5 KiB
Devicetree
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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//
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// Copyright 2024 Comvetia AG
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/dts-v1/;
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#include "imx6q-phytec-pfla02.dtsi"
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/ {
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model = "COMVETIA QSoIP LXR-2";
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compatible = "comvetia,imx6q-lxr", "phytec,imx6q-pfla02", "fsl,imx6q";
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chosen {
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stdout-path = &uart4;
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};
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spi {
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compatible = "spi-gpio";
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_spi_gpio>;
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sck-gpios = <&gpio5 8 GPIO_ACTIVE_HIGH>;
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mosi-gpios = <&gpio5 7 GPIO_ACTIVE_HIGH>;
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num-chipselects = <0>;
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#address-cells = <1>;
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#size-cells = <0>;
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fpga@0 {
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compatible = "altr,fpga-passive-serial";
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reg = <0>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_fpga>;
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nconfig-gpios = <&gpio4 18 GPIO_ACTIVE_LOW>;
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nstat-gpios = <&gpio4 19 GPIO_ACTIVE_LOW>;
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confd-gpios = <&gpio1 6 GPIO_ACTIVE_HIGH>;
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};
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};
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};
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&ecspi3 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_ecspi3>;
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cs-gpios = <&gpio4 24 GPIO_ACTIVE_LOW>;
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status = "okay";
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flash@0 {
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compatible = "jedec,spi-nor";
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reg = <0>;
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spi-max-frequency = <20000000>;
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};
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};
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&fec {
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status = "okay";
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};
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&i2c3 {
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status = "okay";
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};
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&uart3 {
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status = "okay";
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};
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&uart4 {
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status = "okay";
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};
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&usdhc3 {
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no-1-8-v;
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status = "okay";
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};
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&iomuxc {
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pinctrl_fpga: fpgagrp {
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fsl,pins = <
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MX6QDL_PAD_GPIO_6__GPIO1_IO06 0x1b0b0
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MX6QDL_PAD_DI0_PIN2__GPIO4_IO18 0x1b0b0
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MX6QDL_PAD_DI0_PIN3__GPIO4_IO19 0x1b0b0
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>;
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};
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pinctrl_spi_gpio: spigpiogrp {
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fsl,pins = <
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MX6QDL_PAD_DISP0_DAT14__GPIO5_IO08 0x1b0b0
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MX6QDL_PAD_DISP0_DAT13__GPIO5_IO07 0x1b0b0
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>;
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};
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};
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