Greg Kroah-Hartman
598cf27219
Link: https://lore.kernel.org/r/20260217200002.683975158@linuxfoundation.org Tested-by: Florian Fainelli <florian.fainelli@broadcom.com> Tested-by: Takeshi Ogasawara <takeshi.ogasawara@futuring-girl.com> Tested-by: Peter Schneider <pschneider1968@googlemail.com> Tested-by: Jon Hunter <jonathanh@nvidia.com> Tested-by: Salvatore Bonaccorso <carnil@debian.org> Tested-by: Brett A C Sheffield <bacs@librecast.net> Tested-by: Mark Brown <broonie@kernel.org> Tested-by: Luna Jernberg <droidbittin@gmail.com> Tested-by: Ronald Warsow <rwarsow@gmx.de> Tested-by: Justin M. Forbes <jforbes@fedoraproject.org> Tested-by: Ron Economos <re@w6rz.net> Tested-by: Miguel Ojeda <ojeda@kernel.org> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
85 lines
2.0 KiB
Devicetree
85 lines
2.0 KiB
Devicetree
// SPDX-License-Identifier: GPL-2.0
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/*
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* Device Tree Source for Sunplus SP7021
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*
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* Copyright (C) 2021 Sunplus Technology Co.
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*/
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#include "sunplus-sp7021.dtsi"
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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/ {
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compatible = "sunplus,sp7021-achip", "sunplus,sp7021";
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model = "Sunplus SP7021 (CA7)";
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#address-cells = <1>;
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#size-cells = <1>;
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interrupt-parent = <&gic>;
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu0: cpu@0 {
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compatible = "arm,cortex-a7";
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device_type = "cpu";
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reg = <0>;
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clock-frequency = <931000000>;
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};
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cpu1: cpu@1 {
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compatible = "arm,cortex-a7";
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device_type = "cpu";
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reg = <1>;
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clock-frequency = <931000000>;
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};
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cpu2: cpu@2 {
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compatible = "arm,cortex-a7";
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device_type = "cpu";
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reg = <2>;
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clock-frequency = <931000000>;
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};
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cpu3: cpu@3 {
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compatible = "arm,cortex-a7";
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device_type = "cpu";
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reg = <3>;
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clock-frequency = <931000000>;
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};
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};
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gic: interrupt-controller@9f101000 {
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compatible = "arm,cortex-a7-gic";
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interrupt-controller;
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#interrupt-cells = <3>;
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reg = <0x9f101000 0x1000>,
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<0x9f102000 0x2000>,
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<0x9f104000 0x2000>,
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<0x9f106000 0x2000>;
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};
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timer {
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compatible = "arm,armv7-timer";
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interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
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clock-frequency = <XTAL>;
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arm,cpu-registers-not-fw-configured;
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};
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arm-pmu {
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compatible = "arm,cortex-a7-pmu";
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interrupts = <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
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};
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soc@9c000000 {
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intc: interrupt-controller@780 {
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interrupt-parent = <&gic>;
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interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>, /* EXT_INT0 */
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<GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; /* EXT_INT1 */
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};
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};
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};
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