Greg Kroah-Hartman
598cf27219
Link: https://lore.kernel.org/r/20260217200002.683975158@linuxfoundation.org Tested-by: Florian Fainelli <florian.fainelli@broadcom.com> Tested-by: Takeshi Ogasawara <takeshi.ogasawara@futuring-girl.com> Tested-by: Peter Schneider <pschneider1968@googlemail.com> Tested-by: Jon Hunter <jonathanh@nvidia.com> Tested-by: Salvatore Bonaccorso <carnil@debian.org> Tested-by: Brett A C Sheffield <bacs@librecast.net> Tested-by: Mark Brown <broonie@kernel.org> Tested-by: Luna Jernberg <droidbittin@gmail.com> Tested-by: Ronald Warsow <rwarsow@gmx.de> Tested-by: Justin M. Forbes <jforbes@fedoraproject.org> Tested-by: Ron Economos <re@w6rz.net> Tested-by: Miguel Ojeda <ojeda@kernel.org> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
70 lines
1.2 KiB
Plaintext
70 lines
1.2 KiB
Plaintext
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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/*
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* Device Tree fragment for LS1028A QDS board, serdes 7777
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*
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* Copyright 2019-2021 NXP
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*
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* Requires a LS1028A QDS board without lane B rework.
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* Requires a SCH-30841 card without lane A/C rewire and with a FW with muxing
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* disabled, plugged in slot 1.
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*/
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/dts-v1/;
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/plugin/;
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&mdio_slot1 {
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#address-cells = <1>;
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#size-cells = <0>;
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/* 4 ports on AQR412 */
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slot1_sxgmii0: ethernet-phy@0 {
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reg = <0x0>;
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compatible = "ethernet-phy-ieee802.3-c45";
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};
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slot1_sxgmii1: ethernet-phy@1 {
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reg = <0x1>;
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compatible = "ethernet-phy-ieee802.3-c45";
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};
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slot1_sxgmii2: ethernet-phy@2 {
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reg = <0x2>;
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compatible = "ethernet-phy-ieee802.3-c45";
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};
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slot1_sxgmii3: ethernet-phy@3 {
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reg = <0x3>;
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compatible = "ethernet-phy-ieee802.3-c45";
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};
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};
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&mscc_felix_ports {
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port@0 {
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status = "okay";
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phy-handle = <&slot1_sxgmii0>;
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phy-mode = "2500base-x";
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};
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port@1 {
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status = "okay";
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phy-handle = <&slot1_sxgmii1>;
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phy-mode = "2500base-x";
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};
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port@2 {
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status = "okay";
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phy-handle = <&slot1_sxgmii2>;
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phy-mode = "2500base-x";
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};
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port@3 {
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status = "okay";
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phy-handle = <&slot1_sxgmii3>;
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phy-mode = "2500base-x";
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};
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};
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&mscc_felix {
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status = "okay";
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};
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