Greg Kroah-Hartman
598cf27219
Link: https://lore.kernel.org/r/20260217200002.683975158@linuxfoundation.org Tested-by: Florian Fainelli <florian.fainelli@broadcom.com> Tested-by: Takeshi Ogasawara <takeshi.ogasawara@futuring-girl.com> Tested-by: Peter Schneider <pschneider1968@googlemail.com> Tested-by: Jon Hunter <jonathanh@nvidia.com> Tested-by: Salvatore Bonaccorso <carnil@debian.org> Tested-by: Brett A C Sheffield <bacs@librecast.net> Tested-by: Mark Brown <broonie@kernel.org> Tested-by: Luna Jernberg <droidbittin@gmail.com> Tested-by: Ronald Warsow <rwarsow@gmx.de> Tested-by: Justin M. Forbes <jforbes@fedoraproject.org> Tested-by: Ron Economos <re@w6rz.net> Tested-by: Miguel Ojeda <ojeda@kernel.org> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
57 lines
1.4 KiB
Devicetree
57 lines
1.4 KiB
Devicetree
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright 2020 NXP
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*/
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/dts-v1/;
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#include "imx8mm-evk.dtsi"
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/ {
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model = "FSL i.MX8MM DDR4 EVK with CYW43455 WIFI/BT board";
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compatible = "fsl,imx8mm-ddr4-evk", "fsl,imx8mm";
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leds {
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pinctrl-0 = <&pinctrl_gpio_led_2>;
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status {
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gpios = <&gpio3 4 GPIO_ACTIVE_LOW>;
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};
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};
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};
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&gpmi {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_gpmi_nand>;
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status = "okay";
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};
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&iomuxc {
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pinctrl_gpmi_nand: gpminandgrp {
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fsl,pins = <
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MX8MM_IOMUXC_NAND_ALE_RAWNAND_ALE 0x00000096
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MX8MM_IOMUXC_NAND_CE0_B_RAWNAND_CE0_B 0x00000096
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MX8MM_IOMUXC_NAND_CE1_B_RAWNAND_CE1_B 0x00000096
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MX8MM_IOMUXC_NAND_CLE_RAWNAND_CLE 0x00000096
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MX8MM_IOMUXC_NAND_DATA00_RAWNAND_DATA00 0x00000096
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MX8MM_IOMUXC_NAND_DATA01_RAWNAND_DATA01 0x00000096
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MX8MM_IOMUXC_NAND_DATA02_RAWNAND_DATA02 0x00000096
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MX8MM_IOMUXC_NAND_DATA03_RAWNAND_DATA03 0x00000096
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MX8MM_IOMUXC_NAND_DATA04_RAWNAND_DATA04 0x00000096
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MX8MM_IOMUXC_NAND_DATA05_RAWNAND_DATA05 0x00000096
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MX8MM_IOMUXC_NAND_DATA06_RAWNAND_DATA06 0x00000096
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MX8MM_IOMUXC_NAND_DATA07_RAWNAND_DATA07 0x00000096
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MX8MM_IOMUXC_NAND_RE_B_RAWNAND_RE_B 0x00000096
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MX8MM_IOMUXC_NAND_READY_B_RAWNAND_READY_B 0x00000056
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MX8MM_IOMUXC_NAND_WE_B_RAWNAND_WE_B 0x00000096
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MX8MM_IOMUXC_NAND_WP_B_RAWNAND_WP_B 0x00000096
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>;
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};
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pinctrl_gpio_led_2: gpioled2grp {
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fsl,pins = <
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MX8MM_IOMUXC_NAND_CE3_B_GPIO3_IO4 0x19
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>;
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};
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};
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