Greg Kroah-Hartman
598cf27219
Link: https://lore.kernel.org/r/20260217200002.683975158@linuxfoundation.org Tested-by: Florian Fainelli <florian.fainelli@broadcom.com> Tested-by: Takeshi Ogasawara <takeshi.ogasawara@futuring-girl.com> Tested-by: Peter Schneider <pschneider1968@googlemail.com> Tested-by: Jon Hunter <jonathanh@nvidia.com> Tested-by: Salvatore Bonaccorso <carnil@debian.org> Tested-by: Brett A C Sheffield <bacs@librecast.net> Tested-by: Mark Brown <broonie@kernel.org> Tested-by: Luna Jernberg <droidbittin@gmail.com> Tested-by: Ronald Warsow <rwarsow@gmx.de> Tested-by: Justin M. Forbes <jforbes@fedoraproject.org> Tested-by: Ron Economos <re@w6rz.net> Tested-by: Miguel Ojeda <ojeda@kernel.org> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
72 lines
1.8 KiB
Devicetree
72 lines
1.8 KiB
Devicetree
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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/*
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* Copyright 2025 NXP
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*/
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#include "imx91-pinfunc.h"
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#include "imx91_93_common.dtsi"
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&clk {
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compatible = "fsl,imx91-ccm";
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};
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&ddr_pmu {
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compatible = "fsl,imx91-ddr-pmu", "fsl,imx93-ddr-pmu";
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};
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&eqos {
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clocks = <&clk IMX91_CLK_ENET1_QOS_TSN_GATE>,
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<&clk IMX91_CLK_ENET1_QOS_TSN_GATE>,
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<&clk IMX91_CLK_ENET_TIMER>,
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<&clk IMX91_CLK_ENET1_QOS_TSN>,
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<&clk IMX91_CLK_ENET1_QOS_TSN_GATE>;
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assigned-clocks = <&clk IMX91_CLK_ENET_TIMER>,
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<&clk IMX91_CLK_ENET1_QOS_TSN>;
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assigned-clock-parents = <&clk IMX93_CLK_SYS_PLL_PFD1_DIV2>,
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<&clk IMX93_CLK_SYS_PLL_PFD0_DIV2>;
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assigned-clock-rates = <100000000>, <250000000>;
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};
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&fec {
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clocks = <&clk IMX91_CLK_ENET2_REGULAR_GATE>,
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<&clk IMX91_CLK_ENET2_REGULAR_GATE>,
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<&clk IMX91_CLK_ENET_TIMER>,
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<&clk IMX91_CLK_ENET2_REGULAR>,
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<&clk IMX93_CLK_DUMMY>;
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assigned-clocks = <&clk IMX91_CLK_ENET_TIMER>,
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<&clk IMX91_CLK_ENET2_REGULAR>;
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assigned-clock-parents = <&clk IMX93_CLK_SYS_PLL_PFD1_DIV2>,
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<&clk IMX93_CLK_SYS_PLL_PFD0_DIV2>;
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assigned-clock-rates = <100000000>, <250000000>;
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};
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&i3c1 {
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clocks = <&clk IMX93_CLK_BUS_AON>,
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<&clk IMX93_CLK_I3C1_GATE>,
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<&clk IMX93_CLK_DUMMY>;
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};
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&i3c2 {
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clocks = <&clk IMX93_CLK_BUS_WAKEUP>,
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<&clk IMX93_CLK_I3C2_GATE>,
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<&clk IMX93_CLK_DUMMY>;
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};
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&iomuxc {
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compatible = "fsl,imx91-iomuxc";
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};
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&media_blk_ctrl {
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compatible = "fsl,imx91-media-blk-ctrl", "syscon";
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clocks = <&clk IMX93_CLK_MEDIA_APB>,
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<&clk IMX93_CLK_MEDIA_AXI>,
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<&clk IMX93_CLK_NIC_MEDIA_GATE>,
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<&clk IMX93_CLK_MEDIA_DISP_PIX>,
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<&clk IMX93_CLK_CAM_PIX>,
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<&clk IMX93_CLK_LCDIF_GATE>,
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<&clk IMX93_CLK_ISI_GATE>,
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<&clk IMX93_CLK_MIPI_CSI_GATE>;
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clock-names = "apb", "axi", "nic", "disp", "cam",
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"lcdif", "isi", "csi";
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};
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