Greg Kroah-Hartman
598cf27219
Link: https://lore.kernel.org/r/20260217200002.683975158@linuxfoundation.org Tested-by: Florian Fainelli <florian.fainelli@broadcom.com> Tested-by: Takeshi Ogasawara <takeshi.ogasawara@futuring-girl.com> Tested-by: Peter Schneider <pschneider1968@googlemail.com> Tested-by: Jon Hunter <jonathanh@nvidia.com> Tested-by: Salvatore Bonaccorso <carnil@debian.org> Tested-by: Brett A C Sheffield <bacs@librecast.net> Tested-by: Mark Brown <broonie@kernel.org> Tested-by: Luna Jernberg <droidbittin@gmail.com> Tested-by: Ronald Warsow <rwarsow@gmx.de> Tested-by: Justin M. Forbes <jforbes@fedoraproject.org> Tested-by: Ron Economos <re@w6rz.net> Tested-by: Miguel Ojeda <ojeda@kernel.org> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
79 lines
1.8 KiB
Devicetree
79 lines
1.8 KiB
Devicetree
// SPDX-License-Identifier: GPL-2.0
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// Copyright (c) 2021 Nuvoton Technology tomer.maimon@nuvoton.com
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#include "nuvoton-common-npcm8xx.dtsi"
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/ {
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#address-cells = <2>;
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#size-cells = <2>;
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cpus {
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#address-cells = <2>;
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#size-cells = <0>;
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cpu0: cpu@0 {
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device_type = "cpu";
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compatible = "arm,cortex-a35";
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clocks = <&clk NPCM8XX_CLK_CPU>;
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reg = <0x0 0x0>;
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next-level-cache = <&l2>;
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enable-method = "psci";
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};
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cpu1: cpu@1 {
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device_type = "cpu";
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compatible = "arm,cortex-a35";
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clocks = <&clk NPCM8XX_CLK_CPU>;
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reg = <0x0 0x1>;
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next-level-cache = <&l2>;
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enable-method = "psci";
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};
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cpu2: cpu@2 {
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device_type = "cpu";
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compatible = "arm,cortex-a35";
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clocks = <&clk NPCM8XX_CLK_CPU>;
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reg = <0x0 0x2>;
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next-level-cache = <&l2>;
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enable-method = "psci";
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};
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cpu3: cpu@3 {
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device_type = "cpu";
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compatible = "arm,cortex-a35";
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clocks = <&clk NPCM8XX_CLK_CPU>;
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reg = <0x0 0x3>;
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next-level-cache = <&l2>;
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enable-method = "psci";
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};
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l2: l2-cache {
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compatible = "cache";
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cache-level = <2>;
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cache-unified;
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};
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};
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arm-pmu {
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compatible = "arm,cortex-a35-pmu";
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interrupts = <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
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};
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psci {
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compatible = "arm,psci-1.0";
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method = "smc";
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};
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timer {
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compatible = "arm,armv8-timer";
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interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
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};
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};
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