Greg Kroah-Hartman
598cf27219
Link: https://lore.kernel.org/r/20260217200002.683975158@linuxfoundation.org Tested-by: Florian Fainelli <florian.fainelli@broadcom.com> Tested-by: Takeshi Ogasawara <takeshi.ogasawara@futuring-girl.com> Tested-by: Peter Schneider <pschneider1968@googlemail.com> Tested-by: Jon Hunter <jonathanh@nvidia.com> Tested-by: Salvatore Bonaccorso <carnil@debian.org> Tested-by: Brett A C Sheffield <bacs@librecast.net> Tested-by: Mark Brown <broonie@kernel.org> Tested-by: Luna Jernberg <droidbittin@gmail.com> Tested-by: Ronald Warsow <rwarsow@gmx.de> Tested-by: Justin M. Forbes <jforbes@fedoraproject.org> Tested-by: Ron Economos <re@w6rz.net> Tested-by: Miguel Ojeda <ojeda@kernel.org> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
61 lines
1.5 KiB
Devicetree
61 lines
1.5 KiB
Devicetree
// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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/*
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* Device Tree Source for the RZ/G2LC SMARC EVK board
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*
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* Copyright (C) 2021 Renesas Electronics Corp.
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*/
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/dts-v1/;
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/*
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* DIP-Switch SW1 setting on SoM
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* 1 : High; 0: Low
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* SW1-2 : SW_SD0_DEV_SEL (1: eMMC; 0: uSD)
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* SW1-3 : SW_SCIF_CAN (1: CAN1; 0: SCIF1)
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* SW1-4 : SW_RSPI_CAN (1: CAN1; 0: RSPI1)
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* SW1-5 : SW_I2S0_I2S1 (1: I2S2 (HDMI audio); 0: I2S0)
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* Please change below macros according to SW1 setting
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*/
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#define SW_SD0_DEV_SEL 1
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#define SW_SCIF_CAN 0
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#if (SW_SCIF_CAN)
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/* Due to HW routing, SW_RSPI_CAN is always 0 when SW_SCIF_CAN is set to 1 */
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#define SW_RSPI_CAN 0
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#else
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/* Please set SW_RSPI_CAN. Default value is 1 */
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#define SW_RSPI_CAN 1
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#endif
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#if (SW_SCIF_CAN && SW_RSPI_CAN)
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#error "Can not set 1 to both SW_SCIF_CAN and SW_RSPI_CAN due to HW routing"
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#endif
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/* comment the #define statement to disable SCIF1 (SER0) on PMOD1 (CN7) */
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#define PMOD1_SER0 1
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/*
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* To enable MTU3a PWM on PMOD0,
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* - Set DIP-Switch SW1-4 to Off position.
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* - Set SW_RSPI_CAN macro to 0.
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* - Set PMOD_MTU3 macro to 1.
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*/
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#define PMOD_MTU3 0
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#if (PMOD_MTU3 && SW_RSPI_CAN)
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#error "Cannot set as both PMOD_MTU3 and SW_RSPI_CAN are mutually exclusive"
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#endif
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/* Please set SW_I2S0_I2S1. Default value is 0 */
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#define SW_I2S0_I2S1 0
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#include "r9a07g044c2.dtsi"
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#include "rzg2lc-smarc-som.dtsi"
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#include "rzg2lc-smarc.dtsi"
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/ {
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model = "Renesas SMARC EVK based on r9a07g044c2";
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compatible = "renesas,smarc-evk", "renesas,r9a07g044c2", "renesas,r9a07g044";
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};
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