Greg Kroah-Hartman
598cf27219
Link: https://lore.kernel.org/r/20260217200002.683975158@linuxfoundation.org Tested-by: Florian Fainelli <florian.fainelli@broadcom.com> Tested-by: Takeshi Ogasawara <takeshi.ogasawara@futuring-girl.com> Tested-by: Peter Schneider <pschneider1968@googlemail.com> Tested-by: Jon Hunter <jonathanh@nvidia.com> Tested-by: Salvatore Bonaccorso <carnil@debian.org> Tested-by: Brett A C Sheffield <bacs@librecast.net> Tested-by: Mark Brown <broonie@kernel.org> Tested-by: Luna Jernberg <droidbittin@gmail.com> Tested-by: Ronald Warsow <rwarsow@gmx.de> Tested-by: Justin M. Forbes <jforbes@fedoraproject.org> Tested-by: Ron Economos <re@w6rz.net> Tested-by: Miguel Ojeda <ojeda@kernel.org> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
101 lines
2.9 KiB
C
101 lines
2.9 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Atomic operations (LLSC).
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*
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* Copyright (C) 2024-2025 Loongson Technology Corporation Limited
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*/
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#ifndef _ASM_ATOMIC_LLSC_H
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#define _ASM_ATOMIC_LLSC_H
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#include <linux/types.h>
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#include <asm/barrier.h>
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#include <asm/cmpxchg.h>
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#define ATOMIC_OP(op, I, asm_op) \
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static inline void arch_atomic_##op(int i, atomic_t *v) \
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{ \
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int temp; \
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\
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__asm__ __volatile__( \
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"1: ll.w %0, %1 #atomic_" #op " \n" \
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" " #asm_op " %0, %0, %2 \n" \
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" sc.w %0, %1 \n" \
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" beq %0, $r0, 1b \n" \
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:"=&r" (temp) , "+ZC"(v->counter) \
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:"r" (I) \
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); \
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}
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#define ATOMIC_OP_RETURN(op, I, asm_op) \
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static inline int arch_atomic_##op##_return_relaxed(int i, atomic_t *v) \
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{ \
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int result, temp; \
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\
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__asm__ __volatile__( \
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"1: ll.w %1, %2 # atomic_" #op "_return \n" \
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" " #asm_op " %0, %1, %3 \n" \
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" sc.w %0, %2 \n" \
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" beq %0, $r0 ,1b \n" \
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" " #asm_op " %0, %1, %3 \n" \
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: "=&r" (result), "=&r" (temp), "+ZC"(v->counter) \
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: "r" (I)); \
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\
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return result; \
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}
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#define ATOMIC_FETCH_OP(op, I, asm_op) \
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static inline int arch_atomic_fetch_##op##_relaxed(int i, atomic_t *v) \
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{ \
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int result, temp; \
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\
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__asm__ __volatile__( \
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"1: ll.w %1, %2 # atomic_fetch_" #op " \n" \
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" " #asm_op " %0, %1, %3 \n" \
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" sc.w %0, %2 \n" \
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" beq %0, $r0 ,1b \n" \
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" add.w %0, %1 ,$r0 \n" \
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: "=&r" (result), "=&r" (temp), "+ZC" (v->counter) \
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: "r" (I)); \
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\
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return result; \
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}
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#define ATOMIC_OPS(op,I ,asm_op, c_op) \
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ATOMIC_OP(op, I, asm_op) \
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ATOMIC_OP_RETURN(op, I , asm_op) \
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ATOMIC_FETCH_OP(op, I, asm_op)
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ATOMIC_OPS(add, i , add.w ,+=)
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ATOMIC_OPS(sub, -i , add.w ,+=)
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#define arch_atomic_add_return_relaxed arch_atomic_add_return_relaxed
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#define arch_atomic_sub_return_relaxed arch_atomic_sub_return_relaxed
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#define arch_atomic_fetch_add_relaxed arch_atomic_fetch_add_relaxed
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#define arch_atomic_fetch_sub_relaxed arch_atomic_fetch_sub_relaxed
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#undef ATOMIC_OPS
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#define ATOMIC_OPS(op, I, asm_op) \
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ATOMIC_OP(op, I, asm_op) \
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ATOMIC_FETCH_OP(op, I, asm_op)
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ATOMIC_OPS(and, i, and)
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ATOMIC_OPS(or, i, or)
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ATOMIC_OPS(xor, i, xor)
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#define arch_atomic_fetch_and_relaxed arch_atomic_fetch_and_relaxed
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#define arch_atomic_fetch_or_relaxed arch_atomic_fetch_or_relaxed
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#define arch_atomic_fetch_xor_relaxed arch_atomic_fetch_xor_relaxed
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#undef ATOMIC_OPS
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#undef ATOMIC_FETCH_OP
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#undef ATOMIC_OP_RETURN
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#undef ATOMIC_OP
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#ifdef CONFIG_64BIT
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#error "64-bit LLSC atomic operations are not supported"
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#endif
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#endif /* _ASM_ATOMIC_LLSC_H */
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