Link: https://lore.kernel.org/r/20260217200002.683975158@linuxfoundation.org Tested-by: Florian Fainelli <florian.fainelli@broadcom.com> Tested-by: Takeshi Ogasawara <takeshi.ogasawara@futuring-girl.com> Tested-by: Peter Schneider <pschneider1968@googlemail.com> Tested-by: Jon Hunter <jonathanh@nvidia.com> Tested-by: Salvatore Bonaccorso <carnil@debian.org> Tested-by: Brett A C Sheffield <bacs@librecast.net> Tested-by: Mark Brown <broonie@kernel.org> Tested-by: Luna Jernberg <droidbittin@gmail.com> Tested-by: Ronald Warsow <rwarsow@gmx.de> Tested-by: Justin M. Forbes <jforbes@fedoraproject.org> Tested-by: Ron Economos <re@w6rz.net> Tested-by: Miguel Ojeda <ojeda@kernel.org> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
24 lines
605 B
C
24 lines
605 B
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Microblaze support for cache consistent memory.
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* Copyright (C) 2010 Michal Simek <monstr@monstr.eu>
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* Copyright (C) 2010 PetaLogix
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* Copyright (C) 2005 John Williams <jwilliams@itee.uq.edu.au>
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*/
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#include <linux/kernel.h>
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#include <linux/string.h>
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#include <linux/types.h>
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#include <linux/mm.h>
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#include <linux/init.h>
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#include <linux/dma-map-ops.h>
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#include <asm/cpuinfo.h>
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#include <asm/cacheflush.h>
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void arch_dma_prep_coherent(struct page *page, size_t size)
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{
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phys_addr_t paddr = page_to_phys(page);
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flush_dcache_range(paddr, paddr + size);
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}
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