Greg Kroah-Hartman
598cf27219
Link: https://lore.kernel.org/r/20260217200002.683975158@linuxfoundation.org Tested-by: Florian Fainelli <florian.fainelli@broadcom.com> Tested-by: Takeshi Ogasawara <takeshi.ogasawara@futuring-girl.com> Tested-by: Peter Schneider <pschneider1968@googlemail.com> Tested-by: Jon Hunter <jonathanh@nvidia.com> Tested-by: Salvatore Bonaccorso <carnil@debian.org> Tested-by: Brett A C Sheffield <bacs@librecast.net> Tested-by: Mark Brown <broonie@kernel.org> Tested-by: Luna Jernberg <droidbittin@gmail.com> Tested-by: Ronald Warsow <rwarsow@gmx.de> Tested-by: Justin M. Forbes <jforbes@fedoraproject.org> Tested-by: Ron Economos <re@w6rz.net> Tested-by: Miguel Ojeda <ojeda@kernel.org> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
30 lines
592 B
C
30 lines
592 B
C
/* SPDX-License-Identifier: GPL-2.0-only */
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#ifndef __ASM_VDSO_PROCESSOR_H
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#define __ASM_VDSO_PROCESSOR_H
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#ifndef __ASSEMBLER__
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#include <asm/barrier.h>
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#include <asm/errata_list.h>
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#include <asm/insn-def.h>
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static inline void cpu_relax(void)
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{
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#ifdef __riscv_muldiv
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int dummy;
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/* In lieu of a halt instruction, induce a long-latency stall. */
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__asm__ __volatile__ ("div %0, %0, zero" : "=r" (dummy));
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#endif
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/*
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* Reduce instruction retirement.
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* This assumes the PC changes.
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*/
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ALT_RISCV_PAUSE();
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barrier();
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}
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#endif /* __ASSEMBLER__ */
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#endif /* __ASM_VDSO_PROCESSOR_H */
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