Greg Kroah-Hartman
598cf27219
Link: https://lore.kernel.org/r/20260217200002.683975158@linuxfoundation.org Tested-by: Florian Fainelli <florian.fainelli@broadcom.com> Tested-by: Takeshi Ogasawara <takeshi.ogasawara@futuring-girl.com> Tested-by: Peter Schneider <pschneider1968@googlemail.com> Tested-by: Jon Hunter <jonathanh@nvidia.com> Tested-by: Salvatore Bonaccorso <carnil@debian.org> Tested-by: Brett A C Sheffield <bacs@librecast.net> Tested-by: Mark Brown <broonie@kernel.org> Tested-by: Luna Jernberg <droidbittin@gmail.com> Tested-by: Ronald Warsow <rwarsow@gmx.de> Tested-by: Justin M. Forbes <jforbes@fedoraproject.org> Tested-by: Ron Economos <re@w6rz.net> Tested-by: Miguel Ojeda <ojeda@kernel.org> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
20 lines
716 B
Plaintext
20 lines
716 B
Plaintext
# SPDX-License-Identifier: GPL-2.0
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config CLK_INTEL_SOCFPGA
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bool "Intel SoCFPGA family clock support" if COMPILE_TEST && !ARCH_INTEL_SOCFPGA
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default ARCH_INTEL_SOCFPGA
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help
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Support for the clock controllers present on Intel SoCFPGA and eASIC
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devices like Aria, Cyclone, Stratix 10, Agilex and N5X eASIC.
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if CLK_INTEL_SOCFPGA
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config CLK_INTEL_SOCFPGA32
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bool "Intel Aria / Cyclone clock controller support" if COMPILE_TEST && (!ARM || !ARCH_INTEL_SOCFPGA)
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default ARM && ARCH_INTEL_SOCFPGA
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config CLK_INTEL_SOCFPGA64
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bool "Intel Stratix / Agilex / N5X / Agilex5 clock controller support" if COMPILE_TEST && (!ARM64 || !ARCH_INTEL_SOCFPGA)
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default ARM64 && ARCH_INTEL_SOCFPGA
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endif # CLK_INTEL_SOCFPGA
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