Link: https://lore.kernel.org/r/20260217200002.683975158@linuxfoundation.org Tested-by: Florian Fainelli <florian.fainelli@broadcom.com> Tested-by: Takeshi Ogasawara <takeshi.ogasawara@futuring-girl.com> Tested-by: Peter Schneider <pschneider1968@googlemail.com> Tested-by: Jon Hunter <jonathanh@nvidia.com> Tested-by: Salvatore Bonaccorso <carnil@debian.org> Tested-by: Brett A C Sheffield <bacs@librecast.net> Tested-by: Mark Brown <broonie@kernel.org> Tested-by: Luna Jernberg <droidbittin@gmail.com> Tested-by: Ronald Warsow <rwarsow@gmx.de> Tested-by: Justin M. Forbes <jforbes@fedoraproject.org> Tested-by: Ron Economos <re@w6rz.net> Tested-by: Miguel Ojeda <ojeda@kernel.org> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
174 lines
4.7 KiB
C
174 lines
4.7 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright 2025 NXP
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*/
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#include <linux/bitfield.h>
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#include <linux/component.h>
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#include <linux/module.h>
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#include <linux/of_platform.h>
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#include <linux/platform_device.h>
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#include <linux/pm_runtime.h>
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#include <linux/regmap.h>
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#include <drm/bridge/dw_hdmi.h>
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#include <sound/asoundef.h>
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#define HTX_PAI_CTRL 0x00
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#define ENABLE BIT(0)
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#define HTX_PAI_CTRL_EXT 0x04
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#define WTMK_HIGH_MASK GENMASK(31, 24)
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#define WTMK_LOW_MASK GENMASK(23, 16)
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#define NUM_CH_MASK GENMASK(10, 8)
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#define WTMK_HIGH(n) FIELD_PREP(WTMK_HIGH_MASK, (n))
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#define WTMK_LOW(n) FIELD_PREP(WTMK_LOW_MASK, (n))
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#define NUM_CH(n) FIELD_PREP(NUM_CH_MASK, (n) - 1)
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#define HTX_PAI_FIELD_CTRL 0x08
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#define PRE_SEL GENMASK(28, 24)
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#define D_SEL GENMASK(23, 20)
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#define V_SEL GENMASK(19, 15)
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#define U_SEL GENMASK(14, 10)
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#define C_SEL GENMASK(9, 5)
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#define P_SEL GENMASK(4, 0)
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struct imx8mp_hdmi_pai {
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struct regmap *regmap;
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struct device *dev;
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};
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static void imx8mp_hdmi_pai_enable(struct dw_hdmi *dw_hdmi, int channel,
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int width, int rate, int non_pcm,
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int iec958)
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{
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const struct dw_hdmi_plat_data *pdata = dw_hdmi_to_plat_data(dw_hdmi);
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struct imx8mp_hdmi_pai *hdmi_pai = pdata->priv_audio;
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int val;
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if (pm_runtime_resume_and_get(hdmi_pai->dev) < 0)
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return;
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/* PAI set control extended */
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val = WTMK_HIGH(3) | WTMK_LOW(3);
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val |= NUM_CH(channel);
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regmap_write(hdmi_pai->regmap, HTX_PAI_CTRL_EXT, val);
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/* IEC60958 format */
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if (iec958) {
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val = FIELD_PREP_CONST(P_SEL,
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__bf_shf(IEC958_SUBFRAME_PARITY));
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val |= FIELD_PREP_CONST(C_SEL,
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__bf_shf(IEC958_SUBFRAME_CHANNEL_STATUS));
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val |= FIELD_PREP_CONST(U_SEL,
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__bf_shf(IEC958_SUBFRAME_USER_DATA));
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val |= FIELD_PREP_CONST(V_SEL,
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__bf_shf(IEC958_SUBFRAME_VALIDITY));
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val |= FIELD_PREP_CONST(D_SEL,
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__bf_shf(IEC958_SUBFRAME_SAMPLE_24_MASK));
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val |= FIELD_PREP_CONST(PRE_SEL,
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__bf_shf(IEC958_SUBFRAME_PREAMBLE_MASK));
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} else {
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/*
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* The allowed PCM widths are 24bit and 32bit, as they are supported
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* by aud2htx module.
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* for 24bit, D_SEL = 0, select all the bits.
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* for 32bit, D_SEL = 8, select 24bit in MSB.
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*/
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val = FIELD_PREP(D_SEL, width - 24);
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}
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regmap_write(hdmi_pai->regmap, HTX_PAI_FIELD_CTRL, val);
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/* PAI start running */
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regmap_write(hdmi_pai->regmap, HTX_PAI_CTRL, ENABLE);
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}
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static void imx8mp_hdmi_pai_disable(struct dw_hdmi *dw_hdmi)
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{
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const struct dw_hdmi_plat_data *pdata = dw_hdmi_to_plat_data(dw_hdmi);
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struct imx8mp_hdmi_pai *hdmi_pai = pdata->priv_audio;
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/* Stop PAI */
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regmap_write(hdmi_pai->regmap, HTX_PAI_CTRL, 0);
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pm_runtime_put_sync(hdmi_pai->dev);
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}
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static const struct regmap_config imx8mp_hdmi_pai_regmap_config = {
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.reg_bits = 32,
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.reg_stride = 4,
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.val_bits = 32,
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.max_register = HTX_PAI_FIELD_CTRL,
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};
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static int imx8mp_hdmi_pai_bind(struct device *dev, struct device *master, void *data)
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{
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struct platform_device *pdev = to_platform_device(dev);
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struct dw_hdmi_plat_data *plat_data = data;
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struct imx8mp_hdmi_pai *hdmi_pai;
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struct resource *res;
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void __iomem *base;
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int ret;
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hdmi_pai = devm_kzalloc(dev, sizeof(*hdmi_pai), GFP_KERNEL);
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if (!hdmi_pai)
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return -ENOMEM;
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base = devm_platform_get_and_ioremap_resource(pdev, 0, &res);
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if (IS_ERR(base))
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return PTR_ERR(base);
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hdmi_pai->regmap = devm_regmap_init_mmio_clk(dev, "apb", base,
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&imx8mp_hdmi_pai_regmap_config);
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if (IS_ERR(hdmi_pai->regmap)) {
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dev_err(dev, "regmap init failed\n");
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return PTR_ERR(hdmi_pai->regmap);
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}
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plat_data->enable_audio = imx8mp_hdmi_pai_enable;
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plat_data->disable_audio = imx8mp_hdmi_pai_disable;
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plat_data->priv_audio = hdmi_pai;
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hdmi_pai->dev = dev;
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ret = devm_pm_runtime_enable(dev);
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if (ret < 0) {
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dev_err(dev, "failed to enable PM runtime: %d\n", ret);
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return ret;
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}
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return 0;
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}
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static const struct component_ops imx8mp_hdmi_pai_ops = {
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.bind = imx8mp_hdmi_pai_bind,
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};
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static int imx8mp_hdmi_pai_probe(struct platform_device *pdev)
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{
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return component_add(&pdev->dev, &imx8mp_hdmi_pai_ops);
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}
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static void imx8mp_hdmi_pai_remove(struct platform_device *pdev)
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{
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component_del(&pdev->dev, &imx8mp_hdmi_pai_ops);
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}
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static const struct of_device_id imx8mp_hdmi_pai_of_table[] = {
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{ .compatible = "fsl,imx8mp-hdmi-pai" },
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{ /* Sentinel */ }
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};
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MODULE_DEVICE_TABLE(of, imx8mp_hdmi_pai_of_table);
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static struct platform_driver imx8mp_hdmi_pai_platform_driver = {
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.probe = imx8mp_hdmi_pai_probe,
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.remove = imx8mp_hdmi_pai_remove,
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.driver = {
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.name = "imx8mp-hdmi-pai",
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.of_match_table = imx8mp_hdmi_pai_of_table,
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},
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};
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module_platform_driver(imx8mp_hdmi_pai_platform_driver);
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MODULE_DESCRIPTION("i.MX8MP HDMI PAI driver");
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MODULE_LICENSE("GPL");
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