Greg Kroah-Hartman
598cf27219
Link: https://lore.kernel.org/r/20260217200002.683975158@linuxfoundation.org Tested-by: Florian Fainelli <florian.fainelli@broadcom.com> Tested-by: Takeshi Ogasawara <takeshi.ogasawara@futuring-girl.com> Tested-by: Peter Schneider <pschneider1968@googlemail.com> Tested-by: Jon Hunter <jonathanh@nvidia.com> Tested-by: Salvatore Bonaccorso <carnil@debian.org> Tested-by: Brett A C Sheffield <bacs@librecast.net> Tested-by: Mark Brown <broonie@kernel.org> Tested-by: Luna Jernberg <droidbittin@gmail.com> Tested-by: Ronald Warsow <rwarsow@gmx.de> Tested-by: Justin M. Forbes <jforbes@fedoraproject.org> Tested-by: Ron Economos <re@w6rz.net> Tested-by: Miguel Ojeda <ojeda@kernel.org> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
44 lines
1.1 KiB
C
44 lines
1.1 KiB
C
/* SPDX-License-Identifier: MIT */
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/*
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* Copyright(c) 2019-2022, Intel Corporation. All rights reserved.
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*/
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#ifndef __INTEL_GSC_DEV_H__
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#define __INTEL_GSC_DEV_H__
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#include <linux/types.h>
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struct drm_i915_private;
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struct intel_gt;
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struct mei_aux_device;
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#define INTEL_GSC_NUM_INTERFACES 2
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/*
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* The HECI1 bit corresponds to bit15 and HECI2 to bit14.
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* The reason for this is to allow growth for more interfaces in the future.
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*/
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#define GSC_IRQ_INTF(_x) BIT(15 - (_x))
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/**
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* struct intel_gsc - graphics security controller
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*
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* @intf: gsc interface
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* @intf.adev: MEI aux. device for this @intf
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* @intf.gem_obj: scratch memory GSC operations
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* @intf.irq: IRQ for this device (%-1 for no IRQ)
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* @intf.id: this interface's id number/index
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*/
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struct intel_gsc {
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struct intel_gsc_intf {
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struct mei_aux_device *adev;
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struct drm_i915_gem_object *gem_obj;
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int irq;
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unsigned int id;
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} intf[INTEL_GSC_NUM_INTERFACES];
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};
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void intel_gsc_init(struct intel_gsc *gsc, struct drm_i915_private *i915);
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void intel_gsc_fini(struct intel_gsc *gsc);
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void intel_gsc_irq_handler(struct intel_gt *gt, u32 iir);
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#endif /* __INTEL_GSC_DEV_H__ */
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