Greg Kroah-Hartman
598cf27219
Link: https://lore.kernel.org/r/20260217200002.683975158@linuxfoundation.org Tested-by: Florian Fainelli <florian.fainelli@broadcom.com> Tested-by: Takeshi Ogasawara <takeshi.ogasawara@futuring-girl.com> Tested-by: Peter Schneider <pschneider1968@googlemail.com> Tested-by: Jon Hunter <jonathanh@nvidia.com> Tested-by: Salvatore Bonaccorso <carnil@debian.org> Tested-by: Brett A C Sheffield <bacs@librecast.net> Tested-by: Mark Brown <broonie@kernel.org> Tested-by: Luna Jernberg <droidbittin@gmail.com> Tested-by: Ronald Warsow <rwarsow@gmx.de> Tested-by: Justin M. Forbes <jforbes@fedoraproject.org> Tested-by: Ron Economos <re@w6rz.net> Tested-by: Miguel Ojeda <ojeda@kernel.org> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
21 lines
620 B
Plaintext
21 lines
620 B
Plaintext
# SPDX-License-Identifier: GPL-2.0-only
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# RISC-V IOMMU support
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config RISCV_IOMMU
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bool "RISC-V IOMMU Support"
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depends on RISCV && 64BIT
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default y
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select IOMMU_API
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help
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Support for implementations of the RISC-V IOMMU architecture that
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complements the RISC-V MMU capabilities, providing similar address
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translation and protection functions for accesses from I/O devices.
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Say Y here if your SoC includes an IOMMU device implementing
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the RISC-V IOMMU architecture.
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config RISCV_IOMMU_PCI
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def_bool y if RISCV_IOMMU && PCI_MSI
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help
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Support for the PCIe implementation of RISC-V IOMMU architecture.
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