Greg Kroah-Hartman
598cf27219
Link: https://lore.kernel.org/r/20260217200002.683975158@linuxfoundation.org Tested-by: Florian Fainelli <florian.fainelli@broadcom.com> Tested-by: Takeshi Ogasawara <takeshi.ogasawara@futuring-girl.com> Tested-by: Peter Schneider <pschneider1968@googlemail.com> Tested-by: Jon Hunter <jonathanh@nvidia.com> Tested-by: Salvatore Bonaccorso <carnil@debian.org> Tested-by: Brett A C Sheffield <bacs@librecast.net> Tested-by: Mark Brown <broonie@kernel.org> Tested-by: Luna Jernberg <droidbittin@gmail.com> Tested-by: Ronald Warsow <rwarsow@gmx.de> Tested-by: Justin M. Forbes <jforbes@fedoraproject.org> Tested-by: Ron Economos <re@w6rz.net> Tested-by: Miguel Ojeda <ojeda@kernel.org> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
72 lines
1.5 KiB
C
72 lines
1.5 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/* Copyright(c) 2020 - 2025 Mucse Corporation. */
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#ifndef _RNPGBE_H
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#define _RNPGBE_H
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#include <linux/types.h>
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#include <linux/mutex.h>
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enum rnpgbe_boards {
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board_n500,
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board_n210
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};
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struct mucse_mbx_info {
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u32 timeout_us;
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u32 delay_us;
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u16 fw_req;
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u16 fw_ack;
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/* lock for only one use mbx */
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struct mutex lock;
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/* fw <--> pf mbx */
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u32 fwpf_shm_base;
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u32 pf2fw_mbx_ctrl;
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u32 fwpf_mbx_mask;
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u32 fwpf_ctrl_base;
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};
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/* Enum for firmware notification modes,
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* more modes (e.g., portup, link_report) will be added in future
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**/
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enum {
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mucse_fw_powerup,
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};
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struct mucse_hw {
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void __iomem *hw_addr;
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struct pci_dev *pdev;
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struct mucse_mbx_info mbx;
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int port;
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u8 pfvfnum;
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};
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struct mucse_stats {
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u64 tx_dropped;
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};
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struct mucse {
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struct net_device *netdev;
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struct pci_dev *pdev;
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struct mucse_hw hw;
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struct mucse_stats stats;
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};
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int rnpgbe_get_permanent_mac(struct mucse_hw *hw, u8 *perm_addr);
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int rnpgbe_reset_hw(struct mucse_hw *hw);
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int rnpgbe_send_notify(struct mucse_hw *hw,
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bool enable,
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int mode);
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int rnpgbe_init_hw(struct mucse_hw *hw, int board_type);
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/* Device IDs */
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#define PCI_VENDOR_ID_MUCSE 0x8848
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#define RNPGBE_DEVICE_ID_N500_QUAD_PORT 0x8308
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#define RNPGBE_DEVICE_ID_N500_DUAL_PORT 0x8318
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#define RNPGBE_DEVICE_ID_N210 0x8208
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#define RNPGBE_DEVICE_ID_N210L 0x820a
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#define mucse_hw_wr32(hw, reg, val) \
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writel((val), (hw)->hw_addr + (reg))
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#endif /* _RNPGBE_H */
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