Greg Kroah-Hartman
598cf27219
Link: https://lore.kernel.org/r/20260217200002.683975158@linuxfoundation.org Tested-by: Florian Fainelli <florian.fainelli@broadcom.com> Tested-by: Takeshi Ogasawara <takeshi.ogasawara@futuring-girl.com> Tested-by: Peter Schneider <pschneider1968@googlemail.com> Tested-by: Jon Hunter <jonathanh@nvidia.com> Tested-by: Salvatore Bonaccorso <carnil@debian.org> Tested-by: Brett A C Sheffield <bacs@librecast.net> Tested-by: Mark Brown <broonie@kernel.org> Tested-by: Luna Jernberg <droidbittin@gmail.com> Tested-by: Ronald Warsow <rwarsow@gmx.de> Tested-by: Justin M. Forbes <jforbes@fedoraproject.org> Tested-by: Ron Economos <re@w6rz.net> Tested-by: Miguel Ojeda <ojeda@kernel.org> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
194 lines
9.1 KiB
C
194 lines
9.1 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Cadence PCIe controller driver.
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*
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* Copyright (c) 2024, Cadence Design Systems
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* Author: Manikandan K Pillai <mpillai@cadence.com>
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*/
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#ifndef _PCIE_CADENCE_HPA_REGS_H
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#define _PCIE_CADENCE_HPA_REGS_H
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#include <linux/kernel.h>
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#include <linux/pci.h>
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#include <linux/pci-epf.h>
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#include <linux/phy/phy.h>
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#include <linux/bitfield.h>
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/* High Performance Architecture (HPA) PCIe controller registers */
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#define CDNS_PCIE_HPA_IP_REG_BANK 0x01000000
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#define CDNS_PCIE_HPA_IP_CFG_CTRL_REG_BANK 0x01003C00
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#define CDNS_PCIE_HPA_IP_AXI_MASTER_COMMON 0x02020000
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/* Address Translation Registers */
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#define CDNS_PCIE_HPA_AXI_SLAVE 0x03000000
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#define CDNS_PCIE_HPA_AXI_MASTER 0x03002000
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/* Root Port register base address */
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#define CDNS_PCIE_HPA_RP_BASE 0x0
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#define CDNS_PCIE_HPA_LM_ID 0x1420
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/* Endpoint Function BARs */
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#define CDNS_PCIE_HPA_LM_EP_FUNC_BAR_CFG(bar, fn) \
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(((bar) < BAR_3) ? CDNS_PCIE_HPA_LM_EP_FUNC_BAR_CFG0(fn) : \
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CDNS_PCIE_HPA_LM_EP_FUNC_BAR_CFG1(fn))
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#define CDNS_PCIE_HPA_LM_EP_FUNC_BAR_CFG0(pfn) (0x4000 * (pfn))
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#define CDNS_PCIE_HPA_LM_EP_FUNC_BAR_CFG1(pfn) ((0x4000 * (pfn)) + 0x04)
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#define CDNS_PCIE_HPA_LM_EP_VFUNC_BAR_CFG(bar, fn) \
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(((bar) < BAR_3) ? CDNS_PCIE_HPA_LM_EP_VFUNC_BAR_CFG0(fn) : \
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CDNS_PCIE_HPA_LM_EP_VFUNC_BAR_CFG1(fn))
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#define CDNS_PCIE_HPA_LM_EP_VFUNC_BAR_CFG0(vfn) ((0x4000 * (vfn)) + 0x08)
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#define CDNS_PCIE_HPA_LM_EP_VFUNC_BAR_CFG1(vfn) ((0x4000 * (vfn)) + 0x0C)
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#define CDNS_PCIE_HPA_LM_EP_FUNC_BAR_CFG_BAR_APERTURE_MASK(f) \
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(GENMASK(5, 0) << (0x4 + (f) * 10))
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#define CDNS_PCIE_HPA_LM_EP_FUNC_BAR_CFG_BAR_APERTURE(b, a) \
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(((a) << (4 + ((b) * 10))) & (CDNS_PCIE_HPA_LM_EP_FUNC_BAR_CFG_BAR_APERTURE_MASK(b)))
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#define CDNS_PCIE_HPA_LM_EP_FUNC_BAR_CFG_BAR_CTRL_MASK(f) \
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(GENMASK(3, 0) << ((f) * 10))
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#define CDNS_PCIE_HPA_LM_EP_FUNC_BAR_CFG_BAR_CTRL(b, c) \
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(((c) << ((b) * 10)) & (CDNS_PCIE_HPA_LM_EP_FUNC_BAR_CFG_BAR_CTRL_MASK(b)))
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/* Endpoint Function Configuration Register */
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#define CDNS_PCIE_HPA_LM_EP_FUNC_CFG 0x02C0
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/* Root Complex BAR Configuration Register */
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#define CDNS_PCIE_HPA_LM_RC_BAR_CFG 0x14
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#define CDNS_PCIE_HPA_LM_RC_BAR_CFG_BAR0_APERTURE_MASK GENMASK(9, 4)
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#define CDNS_PCIE_HPA_LM_RC_BAR_CFG_BAR0_APERTURE(a) \
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FIELD_PREP(CDNS_PCIE_HPA_LM_RC_BAR_CFG_BAR0_APERTURE_MASK, a)
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#define CDNS_PCIE_HPA_LM_RC_BAR_CFG_BAR0_CTRL_MASK GENMASK(3, 0)
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#define CDNS_PCIE_HPA_LM_RC_BAR_CFG_BAR0_CTRL(c) \
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FIELD_PREP(CDNS_PCIE_HPA_LM_RC_BAR_CFG_BAR0_CTRL_MASK, c)
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#define CDNS_PCIE_HPA_LM_RC_BAR_CFG_BAR1_APERTURE_MASK GENMASK(19, 14)
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#define CDNS_PCIE_HPA_LM_RC_BAR_CFG_BAR1_APERTURE(a) \
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FIELD_PREP(CDNS_PCIE_HPA_LM_RC_BAR_CFG_BAR1_APERTURE_MASK, a)
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#define CDNS_PCIE_HPA_LM_RC_BAR_CFG_BAR1_CTRL_MASK GENMASK(13, 10)
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#define CDNS_PCIE_HPA_LM_RC_BAR_CFG_BAR1_CTRL(c) \
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FIELD_PREP(CDNS_PCIE_HPA_LM_RC_BAR_CFG_BAR1_CTRL_MASK, c)
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#define CDNS_PCIE_HPA_LM_RC_BAR_CFG_PREFETCH_MEM_ENABLE BIT(20)
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#define CDNS_PCIE_HPA_LM_RC_BAR_CFG_PREFETCH_MEM_64BITS BIT(21)
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#define CDNS_PCIE_HPA_LM_RC_BAR_CFG_IO_ENABLE BIT(22)
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#define CDNS_PCIE_HPA_LM_RC_BAR_CFG_IO_32BITS BIT(23)
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/* BAR control values applicable to both Endpoint Function and Root Complex */
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#define CDNS_PCIE_HPA_LM_BAR_CFG_CTRL_DISABLED 0x0
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#define CDNS_PCIE_HPA_LM_BAR_CFG_CTRL_IO_32BITS 0x3
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#define CDNS_PCIE_HPA_LM_BAR_CFG_CTRL_MEM_32BITS 0x1
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#define CDNS_PCIE_HPA_LM_BAR_CFG_CTRL_PREFETCH_MEM_32BITS 0x9
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#define CDNS_PCIE_HPA_LM_BAR_CFG_CTRL_MEM_64BITS 0x5
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#define CDNS_PCIE_HPA_LM_BAR_CFG_CTRL_PREFETCH_MEM_64BITS 0xD
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#define HPA_LM_RC_BAR_CFG_CTRL_DISABLED(bar) \
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(CDNS_PCIE_HPA_LM_BAR_CFG_CTRL_DISABLED << ((bar) * 10))
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#define HPA_LM_RC_BAR_CFG_CTRL_IO_32BITS(bar) \
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(CDNS_PCIE_HPA_LM_BAR_CFG_CTRL_IO_32BITS << ((bar) * 10))
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#define HPA_LM_RC_BAR_CFG_CTRL_MEM_32BITS(bar) \
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(CDNS_PCIE_HPA_LM_BAR_CFG_CTRL_MEM_32BITS << ((bar) * 10))
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#define HPA_LM_RC_BAR_CFG_CTRL_PREF_MEM_32BITS(bar) \
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(CDNS_PCIE_HPA_LM_BAR_CFG_CTRL_PREFETCH_MEM_32BITS << ((bar) * 10))
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#define HPA_LM_RC_BAR_CFG_CTRL_MEM_64BITS(bar) \
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(CDNS_PCIE_HPA_LM_BAR_CFG_CTRL_MEM_64BITS << ((bar) * 10))
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#define HPA_LM_RC_BAR_CFG_CTRL_PREF_MEM_64BITS(bar) \
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(CDNS_PCIE_HPA_LM_BAR_CFG_CTRL_PREFETCH_MEM_64BITS << ((bar) * 10))
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#define HPA_LM_RC_BAR_CFG_APERTURE(bar, aperture) \
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(((aperture) - 7) << (((bar) * 10) + 4))
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#define CDNS_PCIE_HPA_LM_PTM_CTRL 0x0520
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#define CDNS_PCIE_HPA_LM_PTM_CTRL_PTMRSEN BIT(17)
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/* Root Port Registers PCI config space for root port function */
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#define CDNS_PCIE_HPA_RP_CAP_OFFSET 0xC0
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/* Region r Outbound AXI to PCIe Address Translation Register 0 */
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#define CDNS_PCIE_HPA_AT_OB_REGION_PCI_ADDR0(r) (0x1010 + ((r) & 0x1F) * 0x0080)
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#define CDNS_PCIE_HPA_AT_OB_REGION_PCI_ADDR0_NBITS_MASK GENMASK(5, 0)
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#define CDNS_PCIE_HPA_AT_OB_REGION_PCI_ADDR0_NBITS(nbits) \
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(((nbits) - 1) & CDNS_PCIE_HPA_AT_OB_REGION_PCI_ADDR0_NBITS_MASK)
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#define CDNS_PCIE_HPA_AT_OB_REGION_PCI_ADDR0_DEVFN_MASK GENMASK(23, 16)
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#define CDNS_PCIE_HPA_AT_OB_REGION_PCI_ADDR0_DEVFN(devfn) \
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FIELD_PREP(CDNS_PCIE_HPA_AT_OB_REGION_PCI_ADDR0_DEVFN_MASK, devfn)
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#define CDNS_PCIE_HPA_AT_OB_REGION_PCI_ADDR0_BUS_MASK GENMASK(31, 24)
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#define CDNS_PCIE_HPA_AT_OB_REGION_PCI_ADDR0_BUS(bus) \
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FIELD_PREP(CDNS_PCIE_HPA_AT_OB_REGION_PCI_ADDR0_BUS_MASK, bus)
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/* Region r Outbound AXI to PCIe Address Translation Register 1 */
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#define CDNS_PCIE_HPA_AT_OB_REGION_PCI_ADDR1(r) (0x1014 + ((r) & 0x1F) * 0x0080)
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/* Region r Outbound PCIe Descriptor Register */
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#define CDNS_PCIE_HPA_AT_OB_REGION_DESC0(r) (0x1008 + ((r) & 0x1F) * 0x0080)
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#define CDNS_PCIE_HPA_AT_OB_REGION_DESC0_TYPE_MASK GENMASK(28, 24)
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#define CDNS_PCIE_HPA_AT_OB_REGION_DESC0_TYPE_MEM \
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FIELD_PREP(CDNS_PCIE_HPA_AT_OB_REGION_DESC0_TYPE_MASK, 0x0)
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#define CDNS_PCIE_HPA_AT_OB_REGION_DESC0_TYPE_IO \
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FIELD_PREP(CDNS_PCIE_HPA_AT_OB_REGION_DESC0_TYPE_MASK, 0x2)
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#define CDNS_PCIE_HPA_AT_OB_REGION_DESC0_TYPE_CONF_TYPE0 \
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FIELD_PREP(CDNS_PCIE_HPA_AT_OB_REGION_DESC0_TYPE_MASK, 0x4)
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#define CDNS_PCIE_HPA_AT_OB_REGION_DESC0_TYPE_CONF_TYPE1 \
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FIELD_PREP(CDNS_PCIE_HPA_AT_OB_REGION_DESC0_TYPE_MASK, 0x5)
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#define CDNS_PCIE_HPA_AT_OB_REGION_DESC0_TYPE_NORMAL_MSG \
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FIELD_PREP(CDNS_PCIE_HPA_AT_OB_REGION_DESC0_TYPE_MASK, 0x10)
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/* Region r Outbound PCIe Descriptor Register */
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#define CDNS_PCIE_HPA_AT_OB_REGION_DESC1(r) (0x100C + ((r) & 0x1F) * 0x0080)
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#define CDNS_PCIE_HPA_AT_OB_REGION_DESC1_BUS_MASK GENMASK(31, 24)
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#define CDNS_PCIE_HPA_AT_OB_REGION_DESC1_BUS(bus) \
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FIELD_PREP(CDNS_PCIE_HPA_AT_OB_REGION_DESC1_BUS_MASK, bus)
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#define CDNS_PCIE_HPA_AT_OB_REGION_DESC1_DEVFN_MASK GENMASK(23, 16)
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#define CDNS_PCIE_HPA_AT_OB_REGION_DESC1_DEVFN(devfn) \
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FIELD_PREP(CDNS_PCIE_HPA_AT_OB_REGION_DESC1_DEVFN_MASK, devfn)
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#define CDNS_PCIE_HPA_AT_OB_REGION_CTRL0(r) (0x1018 + ((r) & 0x1F) * 0x0080)
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#define CDNS_PCIE_HPA_AT_OB_REGION_CTRL0_SUPPLY_BUS BIT(26)
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#define CDNS_PCIE_HPA_AT_OB_REGION_CTRL0_SUPPLY_DEV_FN BIT(25)
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/* Region r AXI Region Base Address Register 0 */
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#define CDNS_PCIE_HPA_AT_OB_REGION_CPU_ADDR0(r) (0x1000 + ((r) & 0x1F) * 0x0080)
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#define CDNS_PCIE_HPA_AT_OB_REGION_CPU_ADDR0_NBITS_MASK GENMASK(5, 0)
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#define CDNS_PCIE_HPA_AT_OB_REGION_CPU_ADDR0_NBITS(nbits) \
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(((nbits) - 1) & CDNS_PCIE_HPA_AT_OB_REGION_CPU_ADDR0_NBITS_MASK)
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/* Region r AXI Region Base Address Register 1 */
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#define CDNS_PCIE_HPA_AT_OB_REGION_CPU_ADDR1(r) (0x1004 + ((r) & 0x1F) * 0x0080)
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/* Root Port BAR Inbound PCIe to AXI Address Translation Register */
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#define CDNS_PCIE_HPA_AT_IB_RP_BAR_ADDR0(bar) (((bar) * 0x0008))
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#define CDNS_PCIE_HPA_AT_IB_RP_BAR_ADDR0_NBITS_MASK GENMASK(5, 0)
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#define CDNS_PCIE_HPA_AT_IB_RP_BAR_ADDR0_NBITS(nbits) \
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(((nbits) - 1) & CDNS_PCIE_HPA_AT_IB_RP_BAR_ADDR0_NBITS_MASK)
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#define CDNS_PCIE_HPA_AT_IB_RP_BAR_ADDR1(bar) (0x04 + ((bar) * 0x0008))
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/* AXI link down register */
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#define CDNS_PCIE_HPA_AT_LINKDOWN 0x04
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/*
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* Physical Layer Configuration Register 0
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* This register contains the parameters required for functional setup
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* of Physical Layer.
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*/
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#define CDNS_PCIE_HPA_PHY_LAYER_CFG0 0x0400
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#define CDNS_PCIE_HPA_DETECT_QUIET_MIN_DELAY_MASK GENMASK(26, 24)
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#define CDNS_PCIE_HPA_DETECT_QUIET_MIN_DELAY(delay) \
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FIELD_PREP(CDNS_PCIE_HPA_DETECT_QUIET_MIN_DELAY_MASK, delay)
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#define CDNS_PCIE_HPA_LINK_TRNG_EN_MASK GENMASK(27, 27)
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#define CDNS_PCIE_HPA_PHY_DBG_STS_REG0 0x0420
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#define CDNS_PCIE_HPA_RP_MAX_IB 0x3
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#define CDNS_PCIE_HPA_MAX_OB 15
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/* Endpoint Function BAR Inbound PCIe to AXI Address Translation Register */
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#define CDNS_PCIE_HPA_AT_IB_EP_FUNC_BAR_ADDR0(fn, bar) (((fn) * 0x0080) + ((bar) * 0x0008))
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#define CDNS_PCIE_HPA_AT_IB_EP_FUNC_BAR_ADDR1(fn, bar) (0x4 + ((fn) * 0x0080) + ((bar) * 0x0008))
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/* Miscellaneous offsets definitions */
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#define CDNS_PCIE_HPA_TAG_MANAGEMENT 0x0
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#define CDNS_PCIE_HPA_SLAVE_RESP 0x100
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#define I_ROOT_PORT_REQ_ID_REG 0x141c
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#define LM_HAL_SBSA_CTRL 0x1170
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#define I_PCIE_BUS_NUMBERS (CDNS_PCIE_HPA_RP_BASE + 0x18)
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#define CDNS_PCIE_EROM 0x18
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#endif /* _PCIE_CADENCE_HPA_REGS_H */
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