Greg Kroah-Hartman
598cf27219
Link: https://lore.kernel.org/r/20260217200002.683975158@linuxfoundation.org Tested-by: Florian Fainelli <florian.fainelli@broadcom.com> Tested-by: Takeshi Ogasawara <takeshi.ogasawara@futuring-girl.com> Tested-by: Peter Schneider <pschneider1968@googlemail.com> Tested-by: Jon Hunter <jonathanh@nvidia.com> Tested-by: Salvatore Bonaccorso <carnil@debian.org> Tested-by: Brett A C Sheffield <bacs@librecast.net> Tested-by: Mark Brown <broonie@kernel.org> Tested-by: Luna Jernberg <droidbittin@gmail.com> Tested-by: Ronald Warsow <rwarsow@gmx.de> Tested-by: Justin M. Forbes <jforbes@fedoraproject.org> Tested-by: Ron Economos <re@w6rz.net> Tested-by: Miguel Ojeda <ojeda@kernel.org> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
72 lines
1.7 KiB
C
72 lines
1.7 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* UFS Host driver for Synopsys Designware Core
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*
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* Copyright (C) 2015-2016 Synopsys, Inc. (www.synopsys.com)
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*
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* Authors: Joao Pinto <jpinto@synopsys.com>
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*/
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#ifndef _UFSHCD_DWC_H
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#define _UFSHCD_DWC_H
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#include <ufs/ufshcd.h>
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/* RMMI Attributes */
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#define CBREFCLKCTRL2 0x8132
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#define CBCRCTRL 0x811F
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#define CBC10DIRECTCONF2 0x810E
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#define CBRATESEL 0x8114
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#define CBCREGADDRLSB 0x8116
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#define CBCREGADDRMSB 0x8117
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#define CBCREGWRLSB 0x8118
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#define CBCREGWRMSB 0x8119
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#define CBCREGRDLSB 0x811A
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#define CBCREGRDMSB 0x811B
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#define CBCREGRDWRSEL 0x811C
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#define CBREFREFCLK_GATE_OVR_EN BIT(7)
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/* M-PHY Attributes */
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#define MTX_FSM_STATE 0x41
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#define MRX_FSM_STATE 0xC1
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/* M-PHY registers */
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#define RX_OVRD_IN_1(n) (0x3006 + ((n) * 0x100))
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#define RX_PCS_OUT(n) (0x300F + ((n) * 0x100))
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#define FAST_FLAGS(n) (0x401C + ((n) * 0x100))
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#define RX_AFE_ATT_IDAC(n) (0x4000 + ((n) * 0x100))
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#define RX_AFE_CTLE_IDAC(n) (0x4001 + ((n) * 0x100))
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#define FW_CALIB_CCFG(n) (0x404D + ((n) * 0x100))
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/* Tx/Rx FSM state */
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enum rx_fsm_state {
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RX_STATE_DISABLED = 0,
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RX_STATE_HIBERN8 = 1,
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RX_STATE_SLEEP = 2,
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RX_STATE_STALL = 3,
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RX_STATE_LSBURST = 4,
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RX_STATE_HSBURST = 5,
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};
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enum tx_fsm_state {
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TX_STATE_DISABLED = 0,
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TX_STATE_HIBERN8 = 1,
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TX_STATE_SLEEP = 2,
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TX_STATE_STALL = 3,
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TX_STATE_LSBURST = 4,
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TX_STATE_HSBURST = 5,
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};
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struct ufshcd_dme_attr_val {
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u32 attr_sel;
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u32 mib_val;
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u8 peer;
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};
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int ufshcd_dwc_link_startup_notify(struct ufs_hba *hba,
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enum ufs_notify_change_status status);
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int ufshcd_dwc_dme_set_attrs(struct ufs_hba *hba,
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const struct ufshcd_dme_attr_val *v, int n);
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#endif /* End of Header */
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