Greg Kroah-Hartman
598cf27219
Link: https://lore.kernel.org/r/20260217200002.683975158@linuxfoundation.org Tested-by: Florian Fainelli <florian.fainelli@broadcom.com> Tested-by: Takeshi Ogasawara <takeshi.ogasawara@futuring-girl.com> Tested-by: Peter Schneider <pschneider1968@googlemail.com> Tested-by: Jon Hunter <jonathanh@nvidia.com> Tested-by: Salvatore Bonaccorso <carnil@debian.org> Tested-by: Brett A C Sheffield <bacs@librecast.net> Tested-by: Mark Brown <broonie@kernel.org> Tested-by: Luna Jernberg <droidbittin@gmail.com> Tested-by: Ronald Warsow <rwarsow@gmx.de> Tested-by: Justin M. Forbes <jforbes@fedoraproject.org> Tested-by: Ron Economos <re@w6rz.net> Tested-by: Miguel Ojeda <ojeda@kernel.org> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
66 lines
2.3 KiB
C
66 lines
2.3 KiB
C
/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
|
|
/*
|
|
* Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
|
|
*/
|
|
|
|
#ifndef _DT_BINDINGS_CLOCK_QCOM_IPQ5424_NSSCC_H
|
|
#define _DT_BINDINGS_CLOCK_QCOM_IPQ5424_NSSCC_H
|
|
|
|
/* NSS_CC clocks */
|
|
#define NSS_CC_CE_APB_CLK 0
|
|
#define NSS_CC_CE_AXI_CLK 1
|
|
#define NSS_CC_CE_CLK_SRC 2
|
|
#define NSS_CC_CFG_CLK_SRC 3
|
|
#define NSS_CC_DEBUG_CLK 4
|
|
#define NSS_CC_EIP_BFDCD_CLK_SRC 5
|
|
#define NSS_CC_EIP_CLK 6
|
|
#define NSS_CC_NSS_CSR_CLK 7
|
|
#define NSS_CC_NSSNOC_CE_APB_CLK 8
|
|
#define NSS_CC_NSSNOC_CE_AXI_CLK 9
|
|
#define NSS_CC_NSSNOC_EIP_CLK 10
|
|
#define NSS_CC_NSSNOC_NSS_CSR_CLK 11
|
|
#define NSS_CC_NSSNOC_PPE_CFG_CLK 12
|
|
#define NSS_CC_NSSNOC_PPE_CLK 13
|
|
#define NSS_CC_PORT1_MAC_CLK 14
|
|
#define NSS_CC_PORT1_RX_CLK 15
|
|
#define NSS_CC_PORT1_RX_CLK_SRC 16
|
|
#define NSS_CC_PORT1_RX_DIV_CLK_SRC 17
|
|
#define NSS_CC_PORT1_TX_CLK 18
|
|
#define NSS_CC_PORT1_TX_CLK_SRC 19
|
|
#define NSS_CC_PORT1_TX_DIV_CLK_SRC 20
|
|
#define NSS_CC_PORT2_MAC_CLK 21
|
|
#define NSS_CC_PORT2_RX_CLK 22
|
|
#define NSS_CC_PORT2_RX_CLK_SRC 23
|
|
#define NSS_CC_PORT2_RX_DIV_CLK_SRC 24
|
|
#define NSS_CC_PORT2_TX_CLK 25
|
|
#define NSS_CC_PORT2_TX_CLK_SRC 26
|
|
#define NSS_CC_PORT2_TX_DIV_CLK_SRC 27
|
|
#define NSS_CC_PORT3_MAC_CLK 28
|
|
#define NSS_CC_PORT3_RX_CLK 29
|
|
#define NSS_CC_PORT3_RX_CLK_SRC 30
|
|
#define NSS_CC_PORT3_RX_DIV_CLK_SRC 31
|
|
#define NSS_CC_PORT3_TX_CLK 32
|
|
#define NSS_CC_PORT3_TX_CLK_SRC 33
|
|
#define NSS_CC_PORT3_TX_DIV_CLK_SRC 34
|
|
#define NSS_CC_PPE_CLK_SRC 35
|
|
#define NSS_CC_PPE_EDMA_CFG_CLK 36
|
|
#define NSS_CC_PPE_EDMA_CLK 37
|
|
#define NSS_CC_PPE_SWITCH_BTQ_CLK 38
|
|
#define NSS_CC_PPE_SWITCH_CFG_CLK 39
|
|
#define NSS_CC_PPE_SWITCH_CLK 40
|
|
#define NSS_CC_PPE_SWITCH_IPE_CLK 41
|
|
#define NSS_CC_UNIPHY_PORT1_RX_CLK 42
|
|
#define NSS_CC_UNIPHY_PORT1_TX_CLK 43
|
|
#define NSS_CC_UNIPHY_PORT2_RX_CLK 44
|
|
#define NSS_CC_UNIPHY_PORT2_TX_CLK 45
|
|
#define NSS_CC_UNIPHY_PORT3_RX_CLK 46
|
|
#define NSS_CC_UNIPHY_PORT3_TX_CLK 47
|
|
#define NSS_CC_XGMAC0_PTP_REF_CLK 48
|
|
#define NSS_CC_XGMAC0_PTP_REF_DIV_CLK_SRC 49
|
|
#define NSS_CC_XGMAC1_PTP_REF_CLK 50
|
|
#define NSS_CC_XGMAC1_PTP_REF_DIV_CLK_SRC 51
|
|
#define NSS_CC_XGMAC2_PTP_REF_CLK 52
|
|
#define NSS_CC_XGMAC2_PTP_REF_DIV_CLK_SRC 53
|
|
|
|
#endif
|