Greg Kroah-Hartman
598cf27219
Link: https://lore.kernel.org/r/20260217200002.683975158@linuxfoundation.org Tested-by: Florian Fainelli <florian.fainelli@broadcom.com> Tested-by: Takeshi Ogasawara <takeshi.ogasawara@futuring-girl.com> Tested-by: Peter Schneider <pschneider1968@googlemail.com> Tested-by: Jon Hunter <jonathanh@nvidia.com> Tested-by: Salvatore Bonaccorso <carnil@debian.org> Tested-by: Brett A C Sheffield <bacs@librecast.net> Tested-by: Mark Brown <broonie@kernel.org> Tested-by: Luna Jernberg <droidbittin@gmail.com> Tested-by: Ronald Warsow <rwarsow@gmx.de> Tested-by: Justin M. Forbes <jforbes@fedoraproject.org> Tested-by: Ron Economos <re@w6rz.net> Tested-by: Miguel Ojeda <ojeda@kernel.org> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
286 lines
7.4 KiB
C
286 lines
7.4 KiB
C
/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
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/*
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* Copyright (c) 2023-2025 Rockchip Electronics Co., Ltd.
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* Author: Finley Xiao <finley.xiao@rock-chips.com>
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*/
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#ifndef _DT_BINDINGS_CLK_ROCKCHIP_RK3506_H
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#define _DT_BINDINGS_CLK_ROCKCHIP_RK3506_H
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/* cru plls */
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#define PLL_GPLL 0
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#define PLL_V0PLL 1
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#define PLL_V1PLL 2
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/* cru-clocks indices */
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#define ARMCLK 3
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#define CLK_DDR 4
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#define XIN24M_GATE 5
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#define CLK_GPLL_GATE 6
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#define CLK_V0PLL_GATE 7
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#define CLK_V1PLL_GATE 8
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#define CLK_GPLL_DIV 9
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#define CLK_GPLL_DIV_100M 10
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#define CLK_V0PLL_DIV 11
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#define CLK_V1PLL_DIV 12
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#define CLK_INT_VOICE_MATRIX0 13
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#define CLK_INT_VOICE_MATRIX1 14
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#define CLK_INT_VOICE_MATRIX2 15
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#define CLK_FRAC_UART_MATRIX0_MUX 16
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#define CLK_FRAC_UART_MATRIX1_MUX 17
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#define CLK_FRAC_VOICE_MATRIX0_MUX 18
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#define CLK_FRAC_VOICE_MATRIX1_MUX 19
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#define CLK_FRAC_COMMON_MATRIX0_MUX 20
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#define CLK_FRAC_COMMON_MATRIX1_MUX 21
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#define CLK_FRAC_COMMON_MATRIX2_MUX 22
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#define CLK_FRAC_UART_MATRIX0 23
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#define CLK_FRAC_UART_MATRIX1 24
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#define CLK_FRAC_VOICE_MATRIX0 25
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#define CLK_FRAC_VOICE_MATRIX1 26
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#define CLK_FRAC_COMMON_MATRIX0 27
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#define CLK_FRAC_COMMON_MATRIX1 28
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#define CLK_FRAC_COMMON_MATRIX2 29
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#define CLK_REF_USBPHY_TOP 30
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#define CLK_REF_DPHY_TOP 31
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#define ACLK_CORE_ROOT 32
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#define PCLK_CORE_ROOT 33
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#define PCLK_DBG 34
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#define PCLK_CORE_GRF 35
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#define PCLK_CORE_CRU 36
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#define CLK_CORE_EMA_DETECT 37
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#define CLK_REF_PVTPLL_CORE 38
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#define PCLK_GPIO1 39
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#define DBCLK_GPIO1 40
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#define ACLK_CORE_PERI_ROOT 41
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#define HCLK_CORE_PERI_ROOT 42
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#define PCLK_CORE_PERI_ROOT 43
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#define CLK_DSMC 44
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#define ACLK_DSMC 45
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#define PCLK_DSMC 46
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#define CLK_FLEXBUS_TX 47
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#define CLK_FLEXBUS_RX 48
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#define ACLK_FLEXBUS 49
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#define HCLK_FLEXBUS 50
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#define ACLK_DSMC_SLV 51
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#define HCLK_DSMC_SLV 52
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#define ACLK_BUS_ROOT 53
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#define HCLK_BUS_ROOT 54
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#define PCLK_BUS_ROOT 55
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#define ACLK_SYSRAM 56
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#define HCLK_SYSRAM 57
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#define ACLK_DMAC0 58
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#define ACLK_DMAC1 59
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#define HCLK_M0 60
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#define PCLK_BUS_GRF 61
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#define PCLK_TIMER 62
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#define CLK_TIMER0_CH0 63
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#define CLK_TIMER0_CH1 64
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#define CLK_TIMER0_CH2 65
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#define CLK_TIMER0_CH3 66
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#define CLK_TIMER0_CH4 67
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#define CLK_TIMER0_CH5 68
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#define PCLK_WDT0 69
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#define TCLK_WDT0 70
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#define PCLK_WDT1 71
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#define TCLK_WDT1 72
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#define PCLK_MAILBOX 73
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#define PCLK_INTMUX 74
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#define PCLK_SPINLOCK 75
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#define PCLK_DDRC 76
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#define HCLK_DDRPHY 77
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#define PCLK_DDRMON 78
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#define CLK_DDRMON_OSC 79
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#define PCLK_STDBY 80
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#define HCLK_USBOTG0 81
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#define HCLK_USBOTG0_PMU 82
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#define CLK_USBOTG0_ADP 83
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#define HCLK_USBOTG1 84
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#define HCLK_USBOTG1_PMU 85
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#define CLK_USBOTG1_ADP 86
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#define PCLK_USBPHY 87
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#define ACLK_DMA2DDR 88
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#define PCLK_DMA2DDR 89
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#define STCLK_M0 90
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#define CLK_DDRPHY 91
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#define CLK_DDRC_SRC 92
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#define ACLK_DDRC_0 93
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#define ACLK_DDRC_1 94
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#define CLK_DDRC 95
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#define CLK_DDRMON 96
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#define HCLK_LSPERI_ROOT 97
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#define PCLK_LSPERI_ROOT 98
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#define PCLK_UART0 99
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#define PCLK_UART1 100
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#define PCLK_UART2 101
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#define PCLK_UART3 102
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#define PCLK_UART4 103
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#define SCLK_UART0 104
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#define SCLK_UART1 105
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#define SCLK_UART2 106
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#define SCLK_UART3 107
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#define SCLK_UART4 108
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#define PCLK_I2C0 109
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#define CLK_I2C0 110
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#define PCLK_I2C1 111
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#define CLK_I2C1 112
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#define PCLK_I2C2 113
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#define CLK_I2C2 114
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#define PCLK_PWM1 115
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#define CLK_PWM1 116
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#define CLK_OSC_PWM1 117
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#define CLK_RC_PWM1 118
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#define CLK_FREQ_PWM1 119
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#define CLK_COUNTER_PWM1 120
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#define PCLK_SPI0 121
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#define CLK_SPI0 122
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#define PCLK_SPI1 123
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#define CLK_SPI1 124
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#define PCLK_GPIO2 125
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#define DBCLK_GPIO2 126
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#define PCLK_GPIO3 127
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#define DBCLK_GPIO3 128
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#define PCLK_GPIO4 129
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#define DBCLK_GPIO4 130
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#define HCLK_CAN0 131
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#define CLK_CAN0 132
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#define HCLK_CAN1 133
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#define CLK_CAN1 134
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#define HCLK_PDM 135
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#define MCLK_PDM 136
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#define CLKOUT_PDM 137
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#define MCLK_SPDIFTX 138
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#define HCLK_SPDIFTX 139
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#define HCLK_SPDIFRX 140
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#define MCLK_SPDIFRX 141
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#define MCLK_SAI0 142
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#define HCLK_SAI0 143
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#define MCLK_OUT_SAI0 144
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#define MCLK_SAI1 145
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#define HCLK_SAI1 146
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#define MCLK_OUT_SAI1 147
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#define HCLK_ASRC0 148
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#define CLK_ASRC0 149
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#define HCLK_ASRC1 150
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#define CLK_ASRC1 151
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#define PCLK_CRU 152
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#define PCLK_PMU_ROOT 153
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#define MCLK_ASRC0 154
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#define MCLK_ASRC1 155
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#define MCLK_ASRC2 156
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#define MCLK_ASRC3 157
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#define LRCK_ASRC0_SRC 158
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#define LRCK_ASRC0_DST 159
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#define LRCK_ASRC1_SRC 160
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#define LRCK_ASRC1_DST 161
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#define ACLK_HSPERI_ROOT 162
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#define HCLK_HSPERI_ROOT 163
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#define PCLK_HSPERI_ROOT 164
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#define CCLK_SRC_SDMMC 165
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#define HCLK_SDMMC 166
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#define HCLK_FSPI 167
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#define SCLK_FSPI 168
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#define PCLK_SPI2 169
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#define ACLK_MAC0 170
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#define ACLK_MAC1 171
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#define PCLK_MAC0 172
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#define PCLK_MAC1 173
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#define CLK_MAC_ROOT 174
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#define CLK_MAC0 175
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#define CLK_MAC1 176
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#define MCLK_SAI2 177
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#define HCLK_SAI2 178
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#define MCLK_OUT_SAI2 179
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#define MCLK_SAI3_SRC 180
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#define HCLK_SAI3 181
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#define MCLK_SAI3 182
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#define MCLK_OUT_SAI3 183
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#define MCLK_SAI4_SRC 184
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#define HCLK_SAI4 185
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#define MCLK_SAI4 186
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#define HCLK_DSM 187
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#define MCLK_DSM 188
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#define PCLK_AUDIO_ADC 189
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#define MCLK_AUDIO_ADC 190
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#define MCLK_AUDIO_ADC_DIV4 191
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#define PCLK_SARADC 192
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#define CLK_SARADC 193
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#define PCLK_OTPC_NS 194
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#define CLK_SBPI_OTPC_NS 195
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#define CLK_USER_OTPC_NS 196
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#define PCLK_UART5 197
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#define SCLK_UART5 198
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#define PCLK_GPIO234_IOC 199
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#define CLK_MAC_PTP_ROOT 200
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#define CLK_MAC0_PTP 201
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#define CLK_MAC1_PTP 202
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#define CLK_SPI2 203
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#define ACLK_VIO_ROOT 204
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#define HCLK_VIO_ROOT 205
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#define PCLK_VIO_ROOT 206
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#define HCLK_RGA 207
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#define ACLK_RGA 208
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#define CLK_CORE_RGA 209
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#define ACLK_VOP 210
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#define HCLK_VOP 211
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#define DCLK_VOP 212
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#define PCLK_DPHY 213
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#define PCLK_DSI_HOST 214
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#define PCLK_TSADC 215
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#define CLK_TSADC 216
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#define CLK_TSADC_TSEN 217
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#define PCLK_GPIO1_IOC 218
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#define PCLK_OTPC_S 219
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#define CLK_SBPI_OTPC_S 220
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#define CLK_USER_OTPC_S 221
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#define PCLK_OTP_MASK 222
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#define PCLK_KEYREADER 223
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#define HCLK_BOOTROM 224
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#define PCLK_DDR_SERVICE 225
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#define HCLK_CRYPTO_S 226
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#define HCLK_KEYLAD 227
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#define CLK_CORE_CRYPTO 228
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#define CLK_PKA_CRYPTO 229
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#define CLK_CORE_CRYPTO_S 230
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#define CLK_PKA_CRYPTO_S 231
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#define ACLK_CRYPTO_S 232
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#define HCLK_RNG_S 233
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#define CLK_CORE_CRYPTO_NS 234
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#define CLK_PKA_CRYPTO_NS 235
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#define ACLK_CRYPTO_NS 236
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#define HCLK_CRYPTO_NS 237
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#define HCLK_RNG 238
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#define CLK_PMU 239
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#define PCLK_PMU 240
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#define CLK_PMU_32K 241
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#define PCLK_PMU_CRU 242
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#define PCLK_PMU_GRF 243
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#define PCLK_GPIO0_IOC 244
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#define PCLK_GPIO0 245
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#define DBCLK_GPIO0 246
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#define PCLK_GPIO1_SHADOW 247
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#define DBCLK_GPIO1_SHADOW 248
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#define PCLK_PMU_HP_TIMER 249
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#define CLK_PMU_HP_TIMER 250
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#define CLK_PMU_HP_TIMER_32K 251
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#define PCLK_PWM0 252
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#define CLK_PWM0 253
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#define CLK_OSC_PWM0 254
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#define CLK_RC_PWM0 255
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#define CLK_MAC_OUT 256
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#define CLK_REF_OUT0 257
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#define CLK_REF_OUT1 258
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#define CLK_32K_FRAC 259
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#define CLK_32K_RC 260
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#define CLK_32K 261
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#define CLK_32K_PMU 262
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#define PCLK_TOUCH_KEY 263
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#define CLK_TOUCH_KEY 264
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#define CLK_REF_PHY_PLL 265
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#define CLK_REF_PHY_PMU_MUX 266
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#define CLK_WIFI_OUT 267
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#define CLK_V0PLL_REF 268
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#define CLK_V1PLL_REF 269
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#define CLK_32K_FRAC_MUX 270
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#endif
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