Greg Kroah-Hartman
598cf27219
Link: https://lore.kernel.org/r/20260217200002.683975158@linuxfoundation.org Tested-by: Florian Fainelli <florian.fainelli@broadcom.com> Tested-by: Takeshi Ogasawara <takeshi.ogasawara@futuring-girl.com> Tested-by: Peter Schneider <pschneider1968@googlemail.com> Tested-by: Jon Hunter <jonathanh@nvidia.com> Tested-by: Salvatore Bonaccorso <carnil@debian.org> Tested-by: Brett A C Sheffield <bacs@librecast.net> Tested-by: Mark Brown <broonie@kernel.org> Tested-by: Luna Jernberg <droidbittin@gmail.com> Tested-by: Ronald Warsow <rwarsow@gmx.de> Tested-by: Justin M. Forbes <jforbes@fedoraproject.org> Tested-by: Ron Economos <re@w6rz.net> Tested-by: Miguel Ojeda <ojeda@kernel.org> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
393 lines
10 KiB
C
393 lines
10 KiB
C
/* SPDX-License-Identifier: (GPL-2.0-only OR MIT) */
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/*
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* Copyright (c) 2025 Rockchip Electronics Co., Ltd.
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* Author: Elaine Zhang <zhangqing@rock-chips.com>
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*/
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#ifndef _DT_BINDINGS_CLK_ROCKCHIP_RV1126B_H
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#define _DT_BINDINGS_CLK_ROCKCHIP_RV1126B_H
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/* pll clocks */
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#define PLL_GPLL 0
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#define PLL_CPLL 1
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#define PLL_AUPLL 2
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#define ARMCLK 3
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#define SCLK_DDR 4
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/* clk (clocks) */
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#define CLK_CPLL_DIV20 5
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#define CLK_CPLL_DIV10 6
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#define CLK_CPLL_DIV8 7
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#define CLK_GPLL_DIV8 8
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#define CLK_GPLL_DIV6 9
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#define CLK_GPLL_DIV4 10
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#define CLK_CPLL_DIV3 11
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#define CLK_GPLL_DIV3 12
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#define CLK_CPLL_DIV2 13
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#define CLK_GPLL_DIV2 14
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#define CLK_CM_FRAC0 15
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#define CLK_CM_FRAC1 16
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#define CLK_CM_FRAC2 17
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#define CLK_UART_FRAC0 18
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#define CLK_UART_FRAC1 19
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#define CLK_AUDIO_FRAC0 20
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#define CLK_AUDIO_FRAC1 21
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#define CLK_AUDIO_INT0 22
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#define CLK_AUDIO_INT1 23
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#define SCLK_UART0_SRC 24
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#define SCLK_UART1 25
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#define SCLK_UART2 26
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#define SCLK_UART3 27
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#define SCLK_UART4 28
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#define SCLK_UART5 29
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#define SCLK_UART6 30
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#define SCLK_UART7 31
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#define MCLK_SAI0 32
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#define MCLK_SAI1 33
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#define MCLK_SAI2 34
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#define MCLK_PDM 35
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#define CLKOUT_PDM 36
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#define MCLK_ASRC0 37
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#define MCLK_ASRC1 38
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#define MCLK_ASRC2 39
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#define MCLK_ASRC3 40
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#define CLK_ASRC0 41
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#define CLK_ASRC1 42
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#define CLK_CORE_PLL 43
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#define CLK_NPU_PLL 44
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#define CLK_VEPU_PLL 45
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#define CLK_ISP_PLL 46
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#define CLK_AISP_PLL 47
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#define CLK_SARADC0_SRC 48
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#define CLK_SARADC1_SRC 49
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#define CLK_SARADC2_SRC 50
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#define HCLK_NPU_ROOT 51
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#define PCLK_NPU_ROOT 52
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#define ACLK_VEPU_ROOT 53
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#define HCLK_VEPU_ROOT 54
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#define PCLK_VEPU_ROOT 55
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#define CLK_CORE_RGA_SRC 56
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#define ACLK_GMAC_ROOT 57
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#define ACLK_VI_ROOT 58
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#define HCLK_VI_ROOT 59
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#define PCLK_VI_ROOT 60
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#define DCLK_VICAP_ROOT 61
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#define CLK_SYS_DSMC_ROOT 62
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#define ACLK_VDO_ROOT 63
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#define ACLK_RKVDEC_ROOT 64
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#define HCLK_VDO_ROOT 65
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#define PCLK_VDO_ROOT 66
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#define DCLK_OOC_SRC 67
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#define DCLK_VOP 68
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#define DCLK_DECOM_SRC 69
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#define PCLK_DDR_ROOT 70
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#define ACLK_SYSMEM_SRC 71
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#define ACLK_TOP_ROOT 72
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#define ACLK_BUS_ROOT 73
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#define HCLK_BUS_ROOT 74
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#define PCLK_BUS_ROOT 75
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#define CCLK_SDMMC0 76
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#define CCLK_SDMMC1 77
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#define CCLK_EMMC 78
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#define SCLK_2X_FSPI0 79
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#define CLK_GMAC_PTP_REF_SRC 80
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#define CLK_GMAC_125M 81
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#define CLK_TIMER_ROOT 82
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#define TCLK_WDT_NS_SRC 83
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#define TCLK_WDT_S_SRC 84
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#define TCLK_WDT_HPMCU 85
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#define CLK_CAN0 86
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#define CLK_CAN1 87
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#define PCLK_PERI_ROOT 88
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#define ACLK_PERI_ROOT 89
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#define CLK_I2C_BUS_SRC 90
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#define CLK_SPI0 91
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#define CLK_SPI1 92
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#define BUSCLK_PMU_SRC 93
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#define CLK_PWM0 94
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#define CLK_PWM2 95
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#define CLK_PWM3 96
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#define CLK_PKA_RKCE_SRC 97
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#define ACLK_RKCE_SRC 98
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#define ACLK_VCP_ROOT 99
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#define HCLK_VCP_ROOT 100
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#define PCLK_VCP_ROOT 101
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#define CLK_CORE_FEC_SRC 102
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#define CLK_CORE_AVSP_SRC 103
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#define CLK_50M_GMAC_IOBUF_VI 104
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#define PCLK_TOP_ROOT 105
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#define CLK_MIPI0_OUT2IO 106
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#define CLK_MIPI1_OUT2IO 107
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#define CLK_MIPI2_OUT2IO 108
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#define CLK_MIPI3_OUT2IO 109
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#define CLK_CIF_OUT2IO 110
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#define CLK_MAC_OUT2IO 111
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#define MCLK_SAI0_OUT2IO 112
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#define MCLK_SAI1_OUT2IO 113
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#define MCLK_SAI2_OUT2IO 114
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#define CLK_CM_FRAC0_SRC 115
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#define CLK_CM_FRAC1_SRC 116
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#define CLK_CM_FRAC2_SRC 117
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#define CLK_UART_FRAC0_SRC 118
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#define CLK_UART_FRAC1_SRC 119
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#define CLK_AUDIO_FRAC0_SRC 120
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#define CLK_AUDIO_FRAC1_SRC 121
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#define ACLK_NPU_ROOT 122
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#define HCLK_RKNN 123
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#define ACLK_RKNN 124
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#define PCLK_GPIO3 125
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#define DBCLK_GPIO3 126
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#define PCLK_IOC_VCCIO3 127
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#define PCLK_SARADC0 128
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#define CLK_SARADC0 129
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#define HCLK_SDMMC1 130
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#define HCLK_VEPU 131
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#define ACLK_VEPU 132
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#define CLK_CORE_VEPU 133
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#define HCLK_FEC 134
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#define ACLK_FEC 135
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#define CLK_CORE_FEC 136
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#define HCLK_AVSP 137
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#define ACLK_AVSP 138
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#define BUSCLK_PMU1_ROOT 139
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#define HCLK_AISP 140
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#define ACLK_AISP 141
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#define CLK_CORE_AISP 142
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#define CLK_CORE_ISP_ROOT 143
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#define PCLK_DSMC 144
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#define ACLK_DSMC 145
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#define HCLK_CAN0 146
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#define HCLK_CAN1 147
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#define PCLK_GPIO2 148
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#define DBCLK_GPIO2 149
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#define PCLK_GPIO4 150
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#define DBCLK_GPIO4 151
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#define PCLK_GPIO5 152
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#define DBCLK_GPIO5 153
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#define PCLK_GPIO6 154
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#define DBCLK_GPIO6 155
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#define PCLK_GPIO7 156
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#define DBCLK_GPIO7 157
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#define PCLK_IOC_VCCIO2 158
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#define PCLK_IOC_VCCIO4 159
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#define PCLK_IOC_VCCIO5 160
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#define PCLK_IOC_VCCIO6 161
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#define PCLK_IOC_VCCIO7 162
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#define HCLK_ISP 163
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#define ACLK_ISP 164
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#define CLK_CORE_ISP 165
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#define HCLK_VICAP 166
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#define ACLK_VICAP 167
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#define DCLK_VICAP 168
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#define ISP0CLK_VICAP 169
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#define HCLK_VPSS 170
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#define ACLK_VPSS 171
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#define CLK_CORE_VPSS 172
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#define PCLK_CSI2HOST0 173
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#define DCLK_CSI2HOST0 174
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#define PCLK_CSI2HOST1 175
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#define DCLK_CSI2HOST1 176
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#define PCLK_CSI2HOST2 177
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#define DCLK_CSI2HOST2 178
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#define PCLK_CSI2HOST3 179
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#define DCLK_CSI2HOST3 180
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#define HCLK_SDMMC0 181
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#define ACLK_GMAC 182
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#define PCLK_GMAC 183
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#define CLK_GMAC_PTP_REF 184
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#define PCLK_CSIPHY0 185
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#define PCLK_CSIPHY1 186
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#define PCLK_MACPHY 187
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#define PCLK_SARADC1 188
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#define CLK_SARADC1 189
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#define PCLK_SARADC2 190
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#define CLK_SARADC2 191
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#define ACLK_RKVDEC 192
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#define HCLK_RKVDEC 193
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#define CLK_HEVC_CA_RKVDEC 194
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#define ACLK_VOP 195
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#define HCLK_VOP 196
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#define HCLK_RKJPEG 197
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#define ACLK_RKJPEG 198
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#define ACLK_RKMMU_DECOM 199
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#define HCLK_RKMMU_DECOM 200
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#define DCLK_DECOM 201
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#define ACLK_DECOM 202
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#define PCLK_DECOM 203
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#define PCLK_MIPI_DSI 204
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#define PCLK_DSIPHY 205
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#define ACLK_OOC 206
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#define ACLK_SYSMEM 207
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#define PCLK_DDRC 208
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#define PCLK_DDRMON 209
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#define CLK_TIMER_DDRMON 210
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#define PCLK_DFICTRL 211
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#define PCLK_DDRPHY 212
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#define PCLK_DMA2DDR 213
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#define CLK_RCOSC_SRC 214
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#define BUSCLK_PMU_MUX 215
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#define BUSCLK_PMU_ROOT 216
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#define PCLK_PMU 217
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#define CLK_XIN_RC_DIV 218
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#define CLK_32K 219
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#define PCLK_PMU_GPIO0 220
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#define DBCLK_PMU_GPIO0 221
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#define PCLK_PMU_HP_TIMER 222
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#define CLK_PMU_HP_TIMER 223
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#define CLK_PMU_32K_HP_TIMER 224
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#define PCLK_PWM1 225
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#define CLK_PWM1 226
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#define CLK_OSC_PWM1 227
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#define CLK_RC_PWM1 228
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#define CLK_FREQ_PWM1 229
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#define CLK_COUNTER_PWM1 230
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#define PCLK_I2C2 231
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#define CLK_I2C2 232
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#define PCLK_UART0 233
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#define SCLK_UART0 234
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#define PCLK_RCOSC_CTRL 235
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#define CLK_OSC_RCOSC_CTRL 236
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#define CLK_REF_RCOSC_CTRL 237
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#define PCLK_IOC_PMUIO0 238
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#define CLK_REFOUT 239
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#define CLK_PREROLL 240
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#define CLK_PREROLL_32K 241
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#define HCLK_PMU_SRAM 242
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#define PCLK_WDT_LPMCU 243
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#define TCLK_WDT_LPMCU 244
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#define CLK_LPMCU 245
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#define CLK_LPMCU_RTC 246
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#define PCLK_LPMCU_MAILBOX 247
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#define HCLK_OOC 248
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#define PCLK_SPI2AHB 249
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#define HCLK_SPI2AHB 250
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#define HCLK_FSPI1 251
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#define HCLK_XIP_FSPI1 252
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#define SCLK_1X_FSPI1 253
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#define PCLK_IOC_PMUIO1 254
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#define PCLK_AUDIO_ADC_PMU 255
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#define MCLK_AUDIO_ADC_PMU 256
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#define MCLK_AUDIO_ADC_DIV4_PMU 257
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#define MCLK_LPSAI 258
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#define ACLK_GIC400 259
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#define PCLK_WDT_NS 260
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#define TCLK_WDT_NS 261
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#define PCLK_WDT_HPMCU 262
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#define HCLK_CACHE 263
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#define PCLK_HPMCU_MAILBOX 264
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#define PCLK_HPMCU_INTMUX 265
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#define CLK_HPMCU 266
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#define CLK_HPMCU_RTC 267
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#define PCLK_RKDMA 268
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#define ACLK_RKDMA 269
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#define PCLK_DCF 270
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#define ACLK_DCF 271
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#define HCLK_RGA 272
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#define ACLK_RGA 273
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#define CLK_CORE_RGA 274
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#define PCLK_TIMER 275
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#define CLK_TIMER0 276
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#define CLK_TIMER1 277
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#define CLK_TIMER2 278
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#define CLK_TIMER3 279
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#define CLK_TIMER4 280
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#define CLK_TIMER5 281
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#define PCLK_I2C0 282
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#define CLK_I2C0 283
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#define PCLK_I2C1 284
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#define CLK_I2C1 285
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#define PCLK_I2C3 286
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#define CLK_I2C3 287
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#define PCLK_I2C4 288
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#define CLK_I2C4 289
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#define PCLK_I2C5 290
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#define CLK_I2C5 291
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#define PCLK_SPI0 292
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#define PCLK_SPI1 293
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#define PCLK_PWM0 294
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#define CLK_OSC_PWM0 295
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#define CLK_RC_PWM0 296
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#define PCLK_PWM2 297
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#define CLK_OSC_PWM2 298
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#define CLK_RC_PWM2 299
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#define PCLK_PWM3 300
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#define CLK_OSC_PWM3 301
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#define CLK_RC_PWM3 302
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#define PCLK_UART1 303
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#define PCLK_UART2 304
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#define PCLK_UART3 305
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#define PCLK_UART4 306
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#define PCLK_UART5 307
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#define PCLK_UART6 308
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#define PCLK_UART7 309
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#define PCLK_TSADC 310
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#define CLK_TSADC 311
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#define HCLK_SAI0 312
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#define HCLK_SAI1 313
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#define HCLK_SAI2 314
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#define HCLK_RKDSM 315
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#define MCLK_RKDSM 316
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#define HCLK_PDM 317
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#define HCLK_ASRC0 318
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#define HCLK_ASRC1 319
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#define PCLK_AUDIO_ADC_BUS 320
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#define MCLK_AUDIO_ADC_BUS 321
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#define MCLK_AUDIO_ADC_DIV4_BUS 322
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#define PCLK_RKCE 323
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#define HCLK_NS_RKCE 324
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#define PCLK_OTPC_NS 325
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#define CLK_SBPI_OTPC_NS 326
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#define CLK_USER_OTPC_NS 327
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#define CLK_OTPC_ARB 328
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#define PCLK_OTP_MASK 329
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#define CLK_TSADC_PHYCTRL 330
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#define LRCK_SRC_ASRC0 331
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#define LRCK_DST_ASRC0 332
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#define LRCK_SRC_ASRC1 333
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#define LRCK_DST_ASRC1 334
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#define PCLK_KEY_READER 335
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#define ACLK_NSRKCE 336
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#define CLK_PKA_NSRKCE 337
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#define PCLK_RTC_ROOT 338
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#define PCLK_GPIO1 339
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#define DBCLK_GPIO1 340
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#define PCLK_IOC_VCCIO1 341
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#define ACLK_USB3OTG 342
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#define CLK_REF_USB3OTG 343
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#define CLK_SUSPEND_USB3OTG 344
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#define HCLK_USB2HOST 345
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#define HCLK_ARB_USB2HOST 346
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#define PCLK_RTC_TEST 347
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#define HCLK_EMMC 348
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#define HCLK_FSPI0 349
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#define HCLK_XIP_FSPI0 350
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#define PCLK_PIPEPHY 351
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#define PCLK_USB2PHY 352
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#define CLK_REF_PIPEPHY_CPLL_SRC 353
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#define CLK_REF_PIPEPHY 354
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#define HCLK_VPSL 355
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#define ACLK_VPSL 356
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#define CLK_CORE_VPSL 357
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#define CLK_MACPHY 358
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#define HCLK_RKRNG_NS 359
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#define HCLK_RKRNG_S_NS 360
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#define CLK_AISP_PLL_SRC 361
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/* secure clks */
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#define CLK_USER_OTPC_S 362
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#define CLK_SBPI_OTPC_S 363
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#define PCLK_OTPC_S 364
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#define PCLK_KEY_READER_S 365
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#define HCLK_KL_RKCE_S 366
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#define HCLK_RKCE_S 367
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#define PCLK_WDT_S 368
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#define TCLK_WDT_S 369
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#define CLK_STIMER0 370
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#define CLK_STIMER1 371
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#define PLK_STIMER 372
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#define HCLK_RKRNG_S 373
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#define CLK_PKA_RKCE_S 374
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#define ACLK_RKCE_S 375
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#endif
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