Greg Kroah-Hartman
598cf27219
Link: https://lore.kernel.org/r/20260217200002.683975158@linuxfoundation.org Tested-by: Florian Fainelli <florian.fainelli@broadcom.com> Tested-by: Takeshi Ogasawara <takeshi.ogasawara@futuring-girl.com> Tested-by: Peter Schneider <pschneider1968@googlemail.com> Tested-by: Jon Hunter <jonathanh@nvidia.com> Tested-by: Salvatore Bonaccorso <carnil@debian.org> Tested-by: Brett A C Sheffield <bacs@librecast.net> Tested-by: Mark Brown <broonie@kernel.org> Tested-by: Luna Jernberg <droidbittin@gmail.com> Tested-by: Ronald Warsow <rwarsow@gmx.de> Tested-by: Justin M. Forbes <jforbes@fedoraproject.org> Tested-by: Ron Economos <re@w6rz.net> Tested-by: Miguel Ojeda <ojeda@kernel.org> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
52 lines
1.5 KiB
C
52 lines
1.5 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
|
|
|
|
#ifndef _DT_BINDINGS_STE_PRCC_RESET
|
|
#define _DT_BINDINGS_STE_PRCC_RESET
|
|
|
|
#define DB8500_PRCC_1 1
|
|
#define DB8500_PRCC_2 2
|
|
#define DB8500_PRCC_3 3
|
|
#define DB8500_PRCC_6 6
|
|
|
|
/* Reset lines on PRCC 1 */
|
|
#define DB8500_PRCC_1_RESET_UART0 0
|
|
#define DB8500_PRCC_1_RESET_UART1 1
|
|
#define DB8500_PRCC_1_RESET_I2C1 2
|
|
#define DB8500_PRCC_1_RESET_MSP0 3
|
|
#define DB8500_PRCC_1_RESET_MSP1 4
|
|
#define DB8500_PRCC_1_RESET_SDI0 5
|
|
#define DB8500_PRCC_1_RESET_I2C2 6
|
|
#define DB8500_PRCC_1_RESET_SPI3 7
|
|
#define DB8500_PRCC_1_RESET_SLIMBUS0 8
|
|
#define DB8500_PRCC_1_RESET_I2C4 9
|
|
#define DB8500_PRCC_1_RESET_MSP3 10
|
|
#define DB8500_PRCC_1_RESET_PER_MSP3 11
|
|
#define DB8500_PRCC_1_RESET_PER_MSP1 12
|
|
#define DB8500_PRCC_1_RESET_PER_MSP0 13
|
|
#define DB8500_PRCC_1_RESET_PER_SLIMBUS 14
|
|
|
|
/* Reset lines on PRCC 2 */
|
|
#define DB8500_PRCC_2_RESET_I2C3 0
|
|
#define DB8500_PRCC_2_RESET_PWL 1
|
|
#define DB8500_PRCC_2_RESET_SDI4 2
|
|
#define DB8500_PRCC_2_RESET_MSP2 3
|
|
#define DB8500_PRCC_2_RESET_SDI1 4
|
|
#define DB8500_PRCC_2_RESET_SDI3 5
|
|
#define DB8500_PRCC_2_RESET_HSIRX 6
|
|
#define DB8500_PRCC_2_RESET_HSITX 7
|
|
#define DB8500_PRCC_1_RESET_PER_MSP2 8
|
|
|
|
/* Reset lines on PRCC 3 */
|
|
#define DB8500_PRCC_3_RESET_SSP0 1
|
|
#define DB8500_PRCC_3_RESET_SSP1 2
|
|
#define DB8500_PRCC_3_RESET_I2C0 3
|
|
#define DB8500_PRCC_3_RESET_SDI2 4
|
|
#define DB8500_PRCC_3_RESET_SKE 5
|
|
#define DB8500_PRCC_3_RESET_UART2 6
|
|
#define DB8500_PRCC_3_RESET_SDI5 7
|
|
|
|
/* Reset lines on PRCC 6 */
|
|
#define DB8500_PRCC_3_RESET_RNG 0
|
|
|
|
#endif
|