Greg Kroah-Hartman
598cf27219
Link: https://lore.kernel.org/r/20260217200002.683975158@linuxfoundation.org Tested-by: Florian Fainelli <florian.fainelli@broadcom.com> Tested-by: Takeshi Ogasawara <takeshi.ogasawara@futuring-girl.com> Tested-by: Peter Schneider <pschneider1968@googlemail.com> Tested-by: Jon Hunter <jonathanh@nvidia.com> Tested-by: Salvatore Bonaccorso <carnil@debian.org> Tested-by: Brett A C Sheffield <bacs@librecast.net> Tested-by: Mark Brown <broonie@kernel.org> Tested-by: Luna Jernberg <droidbittin@gmail.com> Tested-by: Ronald Warsow <rwarsow@gmx.de> Tested-by: Justin M. Forbes <jforbes@fedoraproject.org> Tested-by: Ron Economos <re@w6rz.net> Tested-by: Miguel Ojeda <ojeda@kernel.org> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
237 lines
8.2 KiB
C
237 lines
8.2 KiB
C
/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
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/*
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* Copyright (c) 2024 Samsung Electronics Co., Ltd.
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* Author: Michal Wilczynski <m.wilczynski@samsung.com>
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*/
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#ifndef _DT_BINDINGS_TH1520_RESET_H
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#define _DT_BINDINGS_TH1520_RESET_H
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/* AO Subsystem */
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#define TH1520_RESET_ID_SYSTEM 0
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#define TH1520_RESET_ID_RTC_APB 1
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#define TH1520_RESET_ID_RTC_REF 2
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#define TH1520_RESET_ID_AOGPIO_DB 3
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#define TH1520_RESET_ID_AOGPIO_APB 4
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#define TH1520_RESET_ID_AOI2C_APB 5
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#define TH1520_RESET_ID_PVT_APB 6
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#define TH1520_RESET_ID_E902_CORE 7
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#define TH1520_RESET_ID_E902_HAD 8
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#define TH1520_RESET_ID_AOTIMER_APB 9
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#define TH1520_RESET_ID_AOTIMER_CORE 10
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#define TH1520_RESET_ID_AOWDT_APB 11
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#define TH1520_RESET_ID_APSYS 12
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#define TH1520_RESET_ID_NPUSYS 13
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#define TH1520_RESET_ID_DDRSYS 14
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#define TH1520_RESET_ID_AXI_AP2CP 15
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#define TH1520_RESET_ID_AXI_CP2AP 16
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#define TH1520_RESET_ID_AXI_CP2SRAM 17
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#define TH1520_RESET_ID_AUDSYS_CORE 18
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#define TH1520_RESET_ID_AUDSYS_IOPMP 19
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#define TH1520_RESET_ID_AUDSYS 20
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#define TH1520_RESET_ID_DSP0 21
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#define TH1520_RESET_ID_DSP1 22
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#define TH1520_RESET_ID_GPU_MODULE 23
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#define TH1520_RESET_ID_VDEC 24
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#define TH1520_RESET_ID_VENC 25
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#define TH1520_RESET_ID_ADC_APB 26
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#define TH1520_RESET_ID_AUDGPIO_DB 27
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#define TH1520_RESET_ID_AUDGPIO_APB 28
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#define TH1520_RESET_ID_AOUART_IF 29
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#define TH1520_RESET_ID_AOUART_APB 30
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#define TH1520_RESET_ID_SRAM_AXI_P0 31
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#define TH1520_RESET_ID_SRAM_AXI_P1 32
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#define TH1520_RESET_ID_SRAM_AXI_P2 33
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#define TH1520_RESET_ID_SRAM_AXI_P3 34
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#define TH1520_RESET_ID_SRAM_AXI_P4 35
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#define TH1520_RESET_ID_SRAM_AXI_CORE 36
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#define TH1520_RESET_ID_SE 37
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/* AP Subsystem */
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#define TH1520_RESET_ID_BROM 0
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#define TH1520_RESET_ID_C910_TOP 1
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#define TH1520_RESET_ID_NPU 2
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#define TH1520_RESET_ID_WDT0 3
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#define TH1520_RESET_ID_WDT1 4
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#define TH1520_RESET_ID_C910_C0 5
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#define TH1520_RESET_ID_C910_C1 6
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#define TH1520_RESET_ID_C910_C2 7
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#define TH1520_RESET_ID_C910_C3 8
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#define TH1520_RESET_ID_CHIP_DBG_CORE 9
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#define TH1520_RESET_ID_CHIP_DBG_AXI 10
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#define TH1520_RESET_ID_AXI4_CPUSYS2_AXI 11
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#define TH1520_RESET_ID_AXI4_CPUSYS2_APB 12
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#define TH1520_RESET_ID_X2H_CPUSYS 13
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#define TH1520_RESET_ID_AHB2_CPUSYS 14
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#define TH1520_RESET_ID_APB3_CPUSYS 15
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#define TH1520_RESET_ID_MBOX0_APB 16
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#define TH1520_RESET_ID_MBOX1_APB 17
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#define TH1520_RESET_ID_MBOX2_APB 18
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#define TH1520_RESET_ID_MBOX3_APB 19
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#define TH1520_RESET_ID_TIMER0_APB 20
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#define TH1520_RESET_ID_TIMER0_CORE 21
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#define TH1520_RESET_ID_TIMER1_APB 22
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#define TH1520_RESET_ID_TIMER1_CORE 23
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#define TH1520_RESET_ID_PERISYS_AHB 24
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#define TH1520_RESET_ID_PERISYS_APB1 25
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#define TH1520_RESET_ID_PERISYS_APB2 26
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#define TH1520_RESET_ID_GMAC0_APB 27
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#define TH1520_RESET_ID_GMAC0_AHB 28
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#define TH1520_RESET_ID_GMAC0_CLKGEN 29
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#define TH1520_RESET_ID_GMAC0_AXI 30
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#define TH1520_RESET_ID_UART0_APB 31
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#define TH1520_RESET_ID_UART0_IF 32
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#define TH1520_RESET_ID_UART1_APB 33
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#define TH1520_RESET_ID_UART1_IF 34
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#define TH1520_RESET_ID_UART2_APB 35
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#define TH1520_RESET_ID_UART2_IF 36
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#define TH1520_RESET_ID_UART3_APB 37
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#define TH1520_RESET_ID_UART3_IF 38
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#define TH1520_RESET_ID_UART4_APB 39
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#define TH1520_RESET_ID_UART4_IF 40
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#define TH1520_RESET_ID_UART5_APB 41
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#define TH1520_RESET_ID_UART5_IF 42
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#define TH1520_RESET_ID_QSPI0_IF 43
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#define TH1520_RESET_ID_QSPI0_APB 44
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#define TH1520_RESET_ID_QSPI1_IF 45
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#define TH1520_RESET_ID_QSPI1_APB 46
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#define TH1520_RESET_ID_SPI_IF 47
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#define TH1520_RESET_ID_SPI_APB 48
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#define TH1520_RESET_ID_I2C0_APB 49
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#define TH1520_RESET_ID_I2C0_CORE 50
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#define TH1520_RESET_ID_I2C1_APB 51
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#define TH1520_RESET_ID_I2C1_CORE 52
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#define TH1520_RESET_ID_I2C2_APB 53
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#define TH1520_RESET_ID_I2C2_CORE 54
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#define TH1520_RESET_ID_I2C3_APB 55
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#define TH1520_RESET_ID_I2C3_CORE 56
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#define TH1520_RESET_ID_I2C4_APB 57
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#define TH1520_RESET_ID_I2C4_CORE 58
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#define TH1520_RESET_ID_I2C5_APB 59
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#define TH1520_RESET_ID_I2C5_CORE 60
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#define TH1520_RESET_ID_GPIO0_DB 61
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#define TH1520_RESET_ID_GPIO0_APB 62
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#define TH1520_RESET_ID_GPIO1_DB 63
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#define TH1520_RESET_ID_GPIO1_APB 64
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#define TH1520_RESET_ID_GPIO2_DB 65
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#define TH1520_RESET_ID_GPIO2_APB 66
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#define TH1520_RESET_ID_PWM_COUNTER 67
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#define TH1520_RESET_ID_PWM_APB 68
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#define TH1520_RESET_ID_PADCTRL0_APB 69
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#define TH1520_RESET_ID_CPU2PERI_X2H 70
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#define TH1520_RESET_ID_CPU2AON_X2H 71
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#define TH1520_RESET_ID_AON2CPU_A2X 72
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#define TH1520_RESET_ID_NPUSYS_AXI 73
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#define TH1520_RESET_ID_NPUSYS_AXI_APB 74
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#define TH1520_RESET_ID_CPU2VP_X2P 75
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#define TH1520_RESET_ID_CPU2VI_X2H 76
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#define TH1520_RESET_ID_BMU_AXI 77
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#define TH1520_RESET_ID_BMU_APB 78
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#define TH1520_RESET_ID_DMAC_CPUSYS_AXI 79
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#define TH1520_RESET_ID_DMAC_CPUSYS_AHB 80
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#define TH1520_RESET_ID_SPINLOCK 81
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#define TH1520_RESET_ID_CFG2TEE 82
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#define TH1520_RESET_ID_DSMART 83
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#define TH1520_RESET_ID_GPIO3_DB 84
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#define TH1520_RESET_ID_GPIO3_APB 85
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#define TH1520_RESET_ID_PERI_I2S 86
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#define TH1520_RESET_ID_PERI_APB3 87
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#define TH1520_RESET_ID_PERI2PERI1_APB 88
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#define TH1520_RESET_ID_VPSYS_APB 89
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#define TH1520_RESET_ID_PERISYS_APB4 90
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#define TH1520_RESET_ID_GMAC1_APB 91
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#define TH1520_RESET_ID_GMAC1_AHB 92
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#define TH1520_RESET_ID_GMAC1_CLKGEN 93
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#define TH1520_RESET_ID_GMAC1_AXI 94
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#define TH1520_RESET_ID_GMAC_AXI 95
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#define TH1520_RESET_ID_GMAC_AXI_APB 96
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#define TH1520_RESET_ID_PADCTRL1_APB 97
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#define TH1520_RESET_ID_VOSYS_AXI 98
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#define TH1520_RESET_ID_VOSYS_AXI_APB 99
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#define TH1520_RESET_ID_VOSYS_AXI_X2X 100
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#define TH1520_RESET_ID_MISC2VP_X2X 101
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#define TH1520_RESET_ID_DSPSYS 102
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#define TH1520_RESET_ID_VISYS 103
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#define TH1520_RESET_ID_VOSYS 104
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#define TH1520_RESET_ID_VPSYS 105
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/* DSP Subsystem */
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#define TH1520_RESET_ID_X2X_DSP1 0
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#define TH1520_RESET_ID_X2X_DSP0 1
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#define TH1520_RESET_ID_X2X_SLAVE_DSP1 2
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#define TH1520_RESET_ID_X2X_SLAVE_DSP0 3
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#define TH1520_RESET_ID_DSP0_CORE 4
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#define TH1520_RESET_ID_DSP0_DEBUG 5
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#define TH1520_RESET_ID_DSP0_APB 6
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#define TH1520_RESET_ID_DSP1_CORE 7
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#define TH1520_RESET_ID_DSP1_DEBUG 8
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#define TH1520_RESET_ID_DSP1_APB 9
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#define TH1520_RESET_ID_DSPSYS_APB 10
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#define TH1520_RESET_ID_AXI4_DSPSYS_SLV 11
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#define TH1520_RESET_ID_AXI4_DSPSYS 12
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#define TH1520_RESET_ID_AXI4_DSP_RS 13
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/* MISC Subsystem */
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#define TH1520_RESET_ID_EMMC_SDIO_CLKGEN 0
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#define TH1520_RESET_ID_EMMC 1
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#define TH1520_RESET_ID_MISCSYS_AXI 2
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#define TH1520_RESET_ID_MISCSYS_AXI_APB 3
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#define TH1520_RESET_ID_SDIO0 4
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#define TH1520_RESET_ID_SDIO1 5
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#define TH1520_RESET_ID_USB3_APB 6
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#define TH1520_RESET_ID_USB3_PHY 7
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#define TH1520_RESET_ID_USB3_VCC 8
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/* VI Subsystem */
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#define TH1520_RESET_ID_ISP0 0
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#define TH1520_RESET_ID_ISP1 1
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#define TH1520_RESET_ID_CSI0_APB 2
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#define TH1520_RESET_ID_CSI1_APB 3
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#define TH1520_RESET_ID_CSI2_APB 4
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#define TH1520_RESET_ID_MIPI_FIFO 5
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#define TH1520_RESET_ID_ISP_VENC_APB 6
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#define TH1520_RESET_ID_VIPRE_APB 7
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#define TH1520_RESET_ID_VIPRE_AXI 8
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#define TH1520_RESET_ID_DW200_APB 9
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#define TH1520_RESET_ID_VISYS3_AXI 10
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#define TH1520_RESET_ID_VISYS2_AXI 11
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#define TH1520_RESET_ID_VISYS1_AXI 12
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#define TH1520_RESET_ID_VISYS_AXI 13
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#define TH1520_RESET_ID_VISYS_APB 14
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#define TH1520_RESET_ID_ISP_VENC_AXI 15
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/* VO Subsystem */
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#define TH1520_RESET_ID_GPU 0
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#define TH1520_RESET_ID_GPU_CLKGEN 1
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#define TH1520_RESET_ID_DPU_AHB 5
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#define TH1520_RESET_ID_DPU_AXI 6
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#define TH1520_RESET_ID_DPU_CORE 7
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#define TH1520_RESET_ID_DSI0_APB 8
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#define TH1520_RESET_ID_DSI1_APB 9
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#define TH1520_RESET_ID_HDMI 10
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#define TH1520_RESET_ID_HDMI_APB 11
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#define TH1520_RESET_ID_VOAXI 12
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#define TH1520_RESET_ID_VOAXI_APB 13
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#define TH1520_RESET_ID_X2H_DPU_AXI 14
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#define TH1520_RESET_ID_X2H_DPU_AHB 15
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#define TH1520_RESET_ID_X2H_DPU1_AXI 16
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#define TH1520_RESET_ID_X2H_DPU1_AHB 17
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/* VP Subsystem */
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#define TH1520_RESET_ID_VPSYS_AXI_APB 0
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#define TH1520_RESET_ID_VPSYS_AXI 1
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#define TH1520_RESET_ID_FCE_APB 2
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#define TH1520_RESET_ID_FCE_CORE 3
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#define TH1520_RESET_ID_FCE_X2X_MASTER 4
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#define TH1520_RESET_ID_FCE_X2X_SLAVE 5
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#define TH1520_RESET_ID_G2D_APB 6
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#define TH1520_RESET_ID_G2D_ACLK 7
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#define TH1520_RESET_ID_G2D_CORE 8
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#define TH1520_RESET_ID_VDEC_APB 9
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#define TH1520_RESET_ID_VDEC_ACLK 10
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#define TH1520_RESET_ID_VDEC_CORE 11
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#define TH1520_RESET_ID_VENC_APB 12
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#define TH1520_RESET_ID_VENC_CORE 13
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#endif /* _DT_BINDINGS_TH1520_RESET_H */
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