Greg Kroah-Hartman
598cf27219
Link: https://lore.kernel.org/r/20260217200002.683975158@linuxfoundation.org Tested-by: Florian Fainelli <florian.fainelli@broadcom.com> Tested-by: Takeshi Ogasawara <takeshi.ogasawara@futuring-girl.com> Tested-by: Peter Schneider <pschneider1968@googlemail.com> Tested-by: Jon Hunter <jonathanh@nvidia.com> Tested-by: Salvatore Bonaccorso <carnil@debian.org> Tested-by: Brett A C Sheffield <bacs@librecast.net> Tested-by: Mark Brown <broonie@kernel.org> Tested-by: Luna Jernberg <droidbittin@gmail.com> Tested-by: Ronald Warsow <rwarsow@gmx.de> Tested-by: Justin M. Forbes <jforbes@fedoraproject.org> Tested-by: Ron Economos <re@w6rz.net> Tested-by: Miguel Ojeda <ojeda@kernel.org> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
39 lines
1.1 KiB
C
39 lines
1.1 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* mt8183-afe-clk.h -- Mediatek 8183 afe clock ctrl definition
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*
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* Copyright (c) 2018 MediaTek Inc.
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* Author: KaiChieh Chuang <kaichieh.chuang@mediatek.com>
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*/
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#ifndef _MT8183_AFE_CLK_H_
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#define _MT8183_AFE_CLK_H_
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/* APLL */
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#define APLL1_W_NAME "APLL1"
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#define APLL2_W_NAME "APLL2"
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enum {
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MT8183_APLL1 = 0,
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MT8183_APLL2,
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};
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struct mtk_base_afe;
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int mt8183_init_clock(struct mtk_base_afe *afe);
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int mt8183_afe_enable_clock(struct mtk_base_afe *afe);
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int mt8183_afe_disable_clock(struct mtk_base_afe *afe);
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int mt8183_apll1_enable(struct mtk_base_afe *afe);
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void mt8183_apll1_disable(struct mtk_base_afe *afe);
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int mt8183_apll2_enable(struct mtk_base_afe *afe);
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void mt8183_apll2_disable(struct mtk_base_afe *afe);
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int mt8183_get_apll_rate(struct mtk_base_afe *afe, int apll);
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int mt8183_get_apll_by_rate(struct mtk_base_afe *afe, int rate);
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int mt8183_get_apll_by_name(struct mtk_base_afe *afe, const char *name);
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int mt8183_mck_enable(struct mtk_base_afe *afe, int mck_id, int rate);
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void mt8183_mck_disable(struct mtk_base_afe *afe, int mck_id);
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#endif
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