Greg Kroah-Hartman
598cf27219
Link: https://lore.kernel.org/r/20260217200002.683975158@linuxfoundation.org Tested-by: Florian Fainelli <florian.fainelli@broadcom.com> Tested-by: Takeshi Ogasawara <takeshi.ogasawara@futuring-girl.com> Tested-by: Peter Schneider <pschneider1968@googlemail.com> Tested-by: Jon Hunter <jonathanh@nvidia.com> Tested-by: Salvatore Bonaccorso <carnil@debian.org> Tested-by: Brett A C Sheffield <bacs@librecast.net> Tested-by: Mark Brown <broonie@kernel.org> Tested-by: Luna Jernberg <droidbittin@gmail.com> Tested-by: Ronald Warsow <rwarsow@gmx.de> Tested-by: Justin M. Forbes <jforbes@fedoraproject.org> Tested-by: Ron Economos <re@w6rz.net> Tested-by: Miguel Ojeda <ojeda@kernel.org> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
61 lines
1.7 KiB
C
61 lines
1.7 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* ALSA SoC Audio Layer - Rockchip SPDIF transceiver driver
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*
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* Copyright (c) 2015 Collabora Ltd.
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* Author: Sjoerd Simons <sjoerd.simons@collabora.co.uk>
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*/
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#ifndef _ROCKCHIP_SPDIF_H
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#define _ROCKCHIP_SPDIF_H
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/*
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* CFGR
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* transfer configuration register
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*/
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#define SPDIF_CFGR_CLK_DIV_SHIFT (16)
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#define SPDIF_CFGR_CLK_DIV_MASK (0xff << SPDIF_CFGR_CLK_DIV_SHIFT)
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#define SPDIF_CFGR_CLK_DIV(x) (x << SPDIF_CFGR_CLK_DIV_SHIFT)
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#define SPDIF_CFGR_HALFWORD_SHIFT 2
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#define SPDIF_CFGR_HALFWORD_DISABLE (0 << SPDIF_CFGR_HALFWORD_SHIFT)
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#define SPDIF_CFGR_HALFWORD_ENABLE (1 << SPDIF_CFGR_HALFWORD_SHIFT)
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#define SPDIF_CFGR_VDW_SHIFT 0
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#define SPDIF_CFGR_VDW(x) (x << SPDIF_CFGR_VDW_SHIFT)
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#define SDPIF_CFGR_VDW_MASK (0xf << SPDIF_CFGR_VDW_SHIFT)
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#define SPDIF_CFGR_VDW_16 SPDIF_CFGR_VDW(0x0)
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#define SPDIF_CFGR_VDW_20 SPDIF_CFGR_VDW(0x1)
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#define SPDIF_CFGR_VDW_24 SPDIF_CFGR_VDW(0x2)
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/*
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* DMACR
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* DMA control register
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*/
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#define SPDIF_DMACR_TDE_SHIFT 5
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#define SPDIF_DMACR_TDE_DISABLE (0 << SPDIF_DMACR_TDE_SHIFT)
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#define SPDIF_DMACR_TDE_ENABLE (1 << SPDIF_DMACR_TDE_SHIFT)
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#define SPDIF_DMACR_TDL_SHIFT 0
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#define SPDIF_DMACR_TDL(x) ((x) << SPDIF_DMACR_TDL_SHIFT)
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#define SPDIF_DMACR_TDL_MASK (0x1f << SPDIF_DMACR_TDL_SHIFT)
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/*
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* XFER
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* Transfer control register
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*/
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#define SPDIF_XFER_TXS_SHIFT 0
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#define SPDIF_XFER_TXS_STOP (0 << SPDIF_XFER_TXS_SHIFT)
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#define SPDIF_XFER_TXS_START (1 << SPDIF_XFER_TXS_SHIFT)
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#define SPDIF_CFGR (0x0000)
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#define SPDIF_SDBLR (0x0004)
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#define SPDIF_DMACR (0x0008)
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#define SPDIF_INTCR (0x000c)
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#define SPDIF_INTSR (0x0010)
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#define SPDIF_XFER (0x0018)
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#define SPDIF_SMPDR (0x0020)
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#endif /* _ROCKCHIP_SPDIF_H */
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