Greg Kroah-Hartman
598cf27219
Link: https://lore.kernel.org/r/20260217200002.683975158@linuxfoundation.org Tested-by: Florian Fainelli <florian.fainelli@broadcom.com> Tested-by: Takeshi Ogasawara <takeshi.ogasawara@futuring-girl.com> Tested-by: Peter Schneider <pschneider1968@googlemail.com> Tested-by: Jon Hunter <jonathanh@nvidia.com> Tested-by: Salvatore Bonaccorso <carnil@debian.org> Tested-by: Brett A C Sheffield <bacs@librecast.net> Tested-by: Mark Brown <broonie@kernel.org> Tested-by: Luna Jernberg <droidbittin@gmail.com> Tested-by: Ronald Warsow <rwarsow@gmx.de> Tested-by: Justin M. Forbes <jforbes@fedoraproject.org> Tested-by: Ron Economos <re@w6rz.net> Tested-by: Miguel Ojeda <ojeda@kernel.org> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
44 lines
2.0 KiB
JSON
44 lines
2.0 KiB
JSON
[
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{
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"BriefDescription": "Counts the total number of BACLEARS due to all branch types including conditional and unconditional jumps, returns, and indirect branches.",
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"Counter": "0,1,2,3,4,5,6,7",
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"EventCode": "0xe6",
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"EventName": "BACLEARS.ANY",
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"PublicDescription": "Counts the total number of BACLEARS, which occur when the Branch Target Buffer (BTB) prediction or lack thereof, was corrected by a later branch predictor in the frontend. Includes BACLEARS due to all branch types including conditional and unconditional jumps, returns, and indirect branches.",
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"SampleAfterValue": "200003",
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"UMask": "0x1"
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},
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{
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"BriefDescription": "Counts the number of instructions retired that were tagged because empty issue slots were seen before the uop due to ITLB miss",
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"Counter": "0,1,2,3,4,5,6,7",
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"EventCode": "0xc6",
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"EventName": "FRONTEND_RETIRED.ITLB_MISS",
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"SampleAfterValue": "1000003",
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"UMask": "0x10"
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},
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{
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"BriefDescription": "Counts every time the code stream enters into a new cache line by walking sequential from the previous line or being redirected by a jump.",
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"Counter": "0,1,2,3,4,5,6,7",
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"EventCode": "0x80",
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"EventName": "ICACHE.ACCESSES",
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"SampleAfterValue": "200003",
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"UMask": "0x3"
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},
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{
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"BriefDescription": "Counts every time the code stream enters into a new cache line by walking sequential from the previous line or being redirected by a jump and the instruction cache registers bytes are not present. -",
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"Counter": "0,1,2,3,4,5,6,7",
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"EventCode": "0x80",
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"EventName": "ICACHE.MISSES",
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"SampleAfterValue": "200003",
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"UMask": "0x2"
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},
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{
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"BriefDescription": "Counts the number of cycles that the micro-sequencer is busy.",
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"Counter": "0,1,2,3,4,5,6,7",
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"EventCode": "0xe7",
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"EventName": "MS_DECODED.MS_BUSY",
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"SampleAfterValue": "1000003",
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"UMask": "0x4"
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}
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]
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