Greg Kroah-Hartman
598cf27219
Link: https://lore.kernel.org/r/20260217200002.683975158@linuxfoundation.org Tested-by: Florian Fainelli <florian.fainelli@broadcom.com> Tested-by: Takeshi Ogasawara <takeshi.ogasawara@futuring-girl.com> Tested-by: Peter Schneider <pschneider1968@googlemail.com> Tested-by: Jon Hunter <jonathanh@nvidia.com> Tested-by: Salvatore Bonaccorso <carnil@debian.org> Tested-by: Brett A C Sheffield <bacs@librecast.net> Tested-by: Mark Brown <broonie@kernel.org> Tested-by: Luna Jernberg <droidbittin@gmail.com> Tested-by: Ronald Warsow <rwarsow@gmx.de> Tested-by: Justin M. Forbes <jforbes@fedoraproject.org> Tested-by: Ron Economos <re@w6rz.net> Tested-by: Miguel Ojeda <ojeda@kernel.org> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
35 lines
760 B
C
35 lines
760 B
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Purna Chandra Mandal,<purna.mandal@microchip.com>
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* Copyright (C) 2015 Microchip Technology Inc. All rights reserved.
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*/
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#ifndef _DT_BINDINGS_CLK_MICROCHIP_PIC32_H_
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#define _DT_BINDINGS_CLK_MICROCHIP_PIC32_H_
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/* clock output indices */
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#define POSCCLK 0
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#define FRCCLK 1
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#define BFRCCLK 2
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#define LPRCCLK 3
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#define SOSCCLK 4
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#define FRCDIVCLK 5
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#define PLLCLK 6
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#define SCLK 7
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#define PB1CLK 8
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#define PB2CLK 9
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#define PB3CLK 10
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#define PB4CLK 11
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#define PB5CLK 12
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#define PB6CLK 13
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#define PB7CLK 14
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#define REF1CLK 15
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#define REF2CLK 16
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#define REF3CLK 17
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#define REF4CLK 18
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#define REF5CLK 19
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#define UPLLCLK 20
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#define MAXCLKS 21
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#endif /* _DT_BINDINGS_CLK_MICROCHIP_PIC32_H_ */
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