Greg Kroah-Hartman
598cf27219
Link: https://lore.kernel.org/r/20260217200002.683975158@linuxfoundation.org Tested-by: Florian Fainelli <florian.fainelli@broadcom.com> Tested-by: Takeshi Ogasawara <takeshi.ogasawara@futuring-girl.com> Tested-by: Peter Schneider <pschneider1968@googlemail.com> Tested-by: Jon Hunter <jonathanh@nvidia.com> Tested-by: Salvatore Bonaccorso <carnil@debian.org> Tested-by: Brett A C Sheffield <bacs@librecast.net> Tested-by: Mark Brown <broonie@kernel.org> Tested-by: Luna Jernberg <droidbittin@gmail.com> Tested-by: Ronald Warsow <rwarsow@gmx.de> Tested-by: Justin M. Forbes <jforbes@fedoraproject.org> Tested-by: Ron Economos <re@w6rz.net> Tested-by: Miguel Ojeda <ojeda@kernel.org> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
29 lines
1.1 KiB
C
29 lines
1.1 KiB
C
/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
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#ifndef __ASM_SH_CPU_FEATURES_H
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#define __ASM_SH_CPU_FEATURES_H
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/*
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* Processor flags
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*
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* Note: When adding a new flag, keep cpu_flags[] in
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* arch/sh/kernel/setup.c in sync so symbolic name
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* mapping of the processor flags has a chance of being
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* reasonably accurate.
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*
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* These flags are also available through the ELF
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* auxiliary vector as AT_HWCAP.
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*/
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#define CPU_HAS_FPU 0x0001 /* Hardware FPU support */
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#define CPU_HAS_P2_FLUSH_BUG 0x0002 /* Need to flush the cache in P2 area */
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#define CPU_HAS_MMU_PAGE_ASSOC 0x0004 /* SH3: TLB way selection bit support */
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#define CPU_HAS_DSP 0x0008 /* SH-DSP: DSP support */
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#define CPU_HAS_PERF_COUNTER 0x0010 /* Hardware performance counters */
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#define CPU_HAS_PTEA 0x0020 /* PTEA register */
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#define CPU_HAS_LLSC 0x0040 /* movli.l/movco.l */
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#define CPU_HAS_L2_CACHE 0x0080 /* Secondary cache / URAM */
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#define CPU_HAS_OP32 0x0100 /* 32-bit instruction support */
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#define CPU_HAS_PTEAEX 0x0200 /* PTE ASID Extension support */
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#define CPU_HAS_CAS_L 0x0400 /* cas.l atomic compare-and-swap */
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#endif /* __ASM_SH_CPU_FEATURES_H */
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