Greg Kroah-Hartman
598cf27219
Link: https://lore.kernel.org/r/20260217200002.683975158@linuxfoundation.org Tested-by: Florian Fainelli <florian.fainelli@broadcom.com> Tested-by: Takeshi Ogasawara <takeshi.ogasawara@futuring-girl.com> Tested-by: Peter Schneider <pschneider1968@googlemail.com> Tested-by: Jon Hunter <jonathanh@nvidia.com> Tested-by: Salvatore Bonaccorso <carnil@debian.org> Tested-by: Brett A C Sheffield <bacs@librecast.net> Tested-by: Mark Brown <broonie@kernel.org> Tested-by: Luna Jernberg <droidbittin@gmail.com> Tested-by: Ronald Warsow <rwarsow@gmx.de> Tested-by: Justin M. Forbes <jforbes@fedoraproject.org> Tested-by: Ron Economos <re@w6rz.net> Tested-by: Miguel Ojeda <ojeda@kernel.org> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
50 lines
1.2 KiB
ArmAsm
50 lines
1.2 KiB
ArmAsm
/*
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* linux/arch/arm/kernel/fiqasm.S
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*
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* Derived from code originally in linux/arch/arm/kernel/fiq.c:
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*
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* Copyright (C) 1998 Russell King
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* Copyright (C) 1998, 1999 Phil Blundell
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* Copyright (C) 2011, Linaro Limited
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*
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* FIQ support written by Philip Blundell <philb@gnu.org>, 1998.
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*
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* FIQ support re-written by Russell King to be more generic
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*
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* v7/Thumb-2 compatibility modifications by Linaro Limited, 2011.
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*/
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#include <linux/linkage.h>
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#include <asm/assembler.h>
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/*
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* Taking an interrupt in FIQ mode is death, so both these functions
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* disable irqs for the duration.
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*/
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ENTRY(__set_fiq_regs)
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mov r2, #PSR_I_BIT | PSR_F_BIT | FIQ_MODE
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mrs r1, cpsr
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msr cpsr_c, r2 @ select FIQ mode
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mov r0, r0 @ avoid hazard prior to ARMv4
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ldmia r0!, {r8 - r12}
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ldr sp, [r0], #4
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ldr lr, [r0]
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msr cpsr_c, r1 @ return to SVC mode
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mov r0, r0 @ avoid hazard prior to ARMv4
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ret lr
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ENDPROC(__set_fiq_regs)
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ENTRY(__get_fiq_regs)
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mov r2, #PSR_I_BIT | PSR_F_BIT | FIQ_MODE
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mrs r1, cpsr
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msr cpsr_c, r2 @ select FIQ mode
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mov r0, r0 @ avoid hazard prior to ARMv4
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stmia r0!, {r8 - r12}
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str sp, [r0], #4
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str lr, [r0]
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msr cpsr_c, r1 @ return to SVC mode
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mov r0, r0 @ avoid hazard prior to ARMv4
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ret lr
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ENDPROC(__get_fiq_regs)
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