Greg Kroah-Hartman
598cf27219
Link: https://lore.kernel.org/r/20260217200002.683975158@linuxfoundation.org Tested-by: Florian Fainelli <florian.fainelli@broadcom.com> Tested-by: Takeshi Ogasawara <takeshi.ogasawara@futuring-girl.com> Tested-by: Peter Schneider <pschneider1968@googlemail.com> Tested-by: Jon Hunter <jonathanh@nvidia.com> Tested-by: Salvatore Bonaccorso <carnil@debian.org> Tested-by: Brett A C Sheffield <bacs@librecast.net> Tested-by: Mark Brown <broonie@kernel.org> Tested-by: Luna Jernberg <droidbittin@gmail.com> Tested-by: Ronald Warsow <rwarsow@gmx.de> Tested-by: Justin M. Forbes <jforbes@fedoraproject.org> Tested-by: Ron Economos <re@w6rz.net> Tested-by: Miguel Ojeda <ojeda@kernel.org> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
29 lines
834 B
C
29 lines
834 B
C
/* SPDX-License-Identifier: GPL-2.0
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*
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* Driver for AMD network controllers and boards
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*
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* Copyright (C) 2021, Xilinx, Inc.
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* Copyright (C) 2022-2023, Advanced Micro Devices, Inc.
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*/
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#ifndef MC_CDX_PCOL_H
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#define MC_CDX_PCOL_H
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#include <linux/cdx/mcdi.h>
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#define MC_CMD_EDAC_GET_DDR_CONFIG_OUT_WORD_LENGTH_LEN 4
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/* Number of registers for the DDR controller */
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#define MC_CMD_GET_DDR_CONFIG_OFST 4
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#define MC_CMD_GET_DDR_CONFIG_LEN 4
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/***********************************/
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/* MC_CMD_EDAC_GET_DDR_CONFIG
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* Provides detailed configuration for the DDR controller of the given index.
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*/
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#define MC_CMD_EDAC_GET_DDR_CONFIG 0x3
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/* MC_CMD_EDAC_GET_DDR_CONFIG_IN msgrequest */
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#define MC_CMD_EDAC_GET_DDR_CONFIG_IN_CONTROLLER_INDEX_OFST 0
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#define MC_CMD_EDAC_GET_DDR_CONFIG_IN_CONTROLLER_INDEX_LEN 4
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#endif /* MC_CDX_PCOL_H */
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