Greg Kroah-Hartman
598cf27219
Link: https://lore.kernel.org/r/20260217200002.683975158@linuxfoundation.org Tested-by: Florian Fainelli <florian.fainelli@broadcom.com> Tested-by: Takeshi Ogasawara <takeshi.ogasawara@futuring-girl.com> Tested-by: Peter Schneider <pschneider1968@googlemail.com> Tested-by: Jon Hunter <jonathanh@nvidia.com> Tested-by: Salvatore Bonaccorso <carnil@debian.org> Tested-by: Brett A C Sheffield <bacs@librecast.net> Tested-by: Mark Brown <broonie@kernel.org> Tested-by: Luna Jernberg <droidbittin@gmail.com> Tested-by: Ronald Warsow <rwarsow@gmx.de> Tested-by: Justin M. Forbes <jforbes@fedoraproject.org> Tested-by: Ron Economos <re@w6rz.net> Tested-by: Miguel Ojeda <ojeda@kernel.org> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
96 lines
2.5 KiB
YAML
96 lines
2.5 KiB
YAML
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/interrupt-controller/fsl,mu-msi.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Freescale/NXP i.MX Messaging Unit (MU) work as msi controller
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maintainers:
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- Frank Li <Frank.Li@nxp.com>
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description: |
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The Messaging Unit module enables two processors within the SoC to
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communicate and coordinate by passing messages (e.g. data, status
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and control) through the MU interface. The MU also provides the ability
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for one processor (A side) to signal the other processor (B side) using
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interrupts.
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Because the MU manages the messaging between processors, the MU uses
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different clocks (from each side of the different peripheral buses).
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Therefore, the MU must synchronize the accesses from one side to the
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other. The MU accomplishes synchronization using two sets of matching
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registers (Processor A-side, Processor B-side).
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MU can work as msi interrupt controller to do doorbell
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allOf:
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- $ref: /schemas/interrupt-controller/msi-controller.yaml#
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properties:
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compatible:
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enum:
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- fsl,imx6sx-mu-msi
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- fsl,imx7ulp-mu-msi
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- fsl,imx8ulp-mu-msi
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- fsl,imx8ulp-mu-msi-s4
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reg:
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items:
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- description: a side register base address
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- description: b side register base address
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reg-names:
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items:
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- const: processor-a-side
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- const: processor-b-side
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interrupts:
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description: a side interrupt number.
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maxItems: 1
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clocks:
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maxItems: 1
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power-domains:
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items:
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- description: a side power domain
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- description: b side power domain
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power-domain-names:
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items:
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- const: processor-a-side
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- const: processor-b-side
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msi-controller: true
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"#msi-cells":
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const: 0
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required:
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- compatible
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- reg
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- interrupts
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- msi-controller
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- "#msi-cells"
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additionalProperties: false
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examples:
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- |
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/firmware/imx/rsrc.h>
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msi-controller@5d270000 {
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compatible = "fsl,imx6sx-mu-msi";
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msi-controller;
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#msi-cells = <0>;
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reg = <0x5d270000 0x10000>, /* A side */
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<0x5d300000 0x10000>; /* B side */
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reg-names = "processor-a-side", "processor-b-side";
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interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>;
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power-domains = <&pd IMX_SC_R_MU_12A>,
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<&pd IMX_SC_R_MU_12B>;
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power-domain-names = "processor-a-side", "processor-b-side";
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};
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